Abstract: A processor to memory interconnect network can be used to construct both small and large scale multiprocessing systems. The interconnect network includes network modules and memory modules. The network and memory modules are constructed of a series of n.times.m switches, each of which route n inputs to m outputs. The switches are designed such that message contention in the interconnect network is reduced. The switches, and thus the memory and network modules are highly modular, thus allowing virtually any scale multiprocessing system to be constructed utilizing the same components.

Abstract: A memory reconfiguration system dynamically configures spare chips into memory during system operation by shifting data around defective chips. The shifting of data around an entire memory chip allows the system to correct bit, addressing, and control errors or faults within the chip. When the system detects an error, or otherwise initiates a memory reconfiguration, it transmits a configuration code to shift registers for a memory write driver. The shift registers, in response to the configuration code, shift write data so that the data is effectively shifted around a particular memory chip and into a spare memory chip. The system selectively transmits the configuration code to shift registers for a memory read driver. Therefore, the system independently shifts data written to the memory inputs and data read from the memory outputs.

Abstract: The invention comprises a plurality of stacked planar processing circuit boards surrounded on at least one side by a plurality of memory boards located substantially perpendicular to the planar processing boards, the processing and memory boards connected by orthogonal interconnect modules. The orthogonal interconnect modules allow closely-spaced orthogonal connection of the processing boards to the memory boards. The memory boards are of a densely packed design having a plurality of removeable memory chip stacks located on the memory boards.

Abstract: The invention comprises a plurality of stacked planar processing circuit boards surrounded on at least one side by a plurality of memory boards located substantially perpendicular to the planar processing boards, the processing and memory boards connected by orthogonal interconnect modules. The orthogonal interconnect modules allow closely-spaced orthogonal connection of the processing boards to the memory boards. The memory boards are of a densely packed design having a plurality of removeable memory chip stacks located on the memory boards.