Abstract: Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

Abstract: A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface, an electrical device coupled to a second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

Abstract: A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

Abstract: Split die IC packages employing a D2D interconnect structure in a die-substrate standoff cavity (i.e., cavity) to provide D2D connections, and related fabrication methods. To facilitate D2D communications between multiple dies in the split die IC package, the package substrate also includes a D2D interconnect structure (e.g., interconnect bridge) that contains D2D interconnects (e.g., metal interconnects) coupled to the multiple dies to provide D2D signal routing between the multiple dies. The D2D interconnect structure is disposed in a cavity that is formed in a die standoff area between the dies and the package substrate as a result of the die interconnects being disposed between the dies and the package substrate standing off the dies from the package substrate. The D2D interconnect structure can be provided in the cavity in the IC package outside of the package substrate to reserve more area in the package substrate for other interconnections.

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

Abstract: Conventional package problems may be overcome with a hybrid metallization and laminate structure that avoids warpage problems and size reduction problems. One example structure may include a metallization structure directly attached to an active side of a logic die stack in a core substrate (on one or both sides of the substrate) with laminate layers built-up on top of the metallization structures for a symmetrical package structure.

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

Abstract: Disclosed is an apparatus and methods for making same. The apparatus includes a substrate, a set of electrical contacts disposed on the surface of the substrate, and an electromagnetic interference (EMI) shield pedestal structure, disposed between an outer periphery of the set of electrical contacts and an outer portion of the substrate.

Abstract: Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for connecting packages for integrated circuits or packaged assemblies with other packages or modules using flex cables. An example packaged assembly for integrated circuits includes: a first integrated circuit (IC) package, a second IC package disposed above the first IC package, and a flex cable, wherein an end of the flex cable is connected to at least one of the first IC package or the second IC package.

Abstract: A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.

Abstract: The present disclosure generally relates to an integrated circuit having a stacked embedded passive substrate (EPS) structure formed therein. In particular, a substrate may have a cavity formed therein and the stacked EPS structure may include multiple passive components formed in the cavity to provide separate electrical paths for decoupling of the integrated circuit. Furthermore, the multiple passive components may each have two respective terminals such that the multiple passive components may support different voltage domains. Among other things, compared to conventional die-side and/or land-side passive components, the stacked EPS structure may advantageously reduce a z-axis height of the integrated circuit, reduce manufacturing costs, improve performance due to shorter electrical paths, and improve design routing through x-axis and y-axis space savings.

Abstract: In conventional panel level packaging, the BGA pad itself can occupy more space on the final connection layer leaving less space to route traces and vias. To address this and other issues, connection pads such as the BGA pad can be split to allow for more efficient routing on the final connection layer.

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.