Patents by Inventor Brigitte Soulier

Brigitte Soulier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230386751
    Abstract: A method for manufacturing an electrical device that includes: anodizing a portion of an anodizable metal layer so as to obtain an anodic porous oxide region and an anodizable metal region adjoining the anodic porous oxide region, the anodic porous oxide region being thicker than the anodizable metal region; depositing a layer of liner material on the anodic porous oxide region and on the anodizable metal region; depositing a layer of filler material on the layer of liner material to obtain a stacked structure having a top surface; planarizing the stacked structure from a top surface thereof until reaching the layer of the liner material, so as to expose a portion of liner material located above at least a portion of the anodic porous oxide region; and removing the exposed portion of liner material.
    Type: Application
    Filed: December 13, 2022
    Publication date: November 30, 2023
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Brigitte SOULIER, Frédéric VOIRON, Julien EL SABAHY
  • Publication number: 20230307185
    Abstract: A capacitor structure that includes a substrate; a conductive layer above the substrate; and a porous layer, above the conductive layer, having pores that extend perpendicularly from a top surface of the porous layer toward the conductive layer. The porous layer comprises a first region in which pores conductive wires are disposed, and a second region in which pores a metal-insulator-metal (MIM) structure is disposed. The first region may be used as a via to contact a bottom electrode of the capacitor structure.
    Type: Application
    Filed: June 2, 2023
    Publication date: September 28, 2023
    Inventors: Frédéric VOIRON, Brigitte SOULIER, Julien EL SABAHY
  • Publication number: 20230245834
    Abstract: An electrical device that includes: a substrate; an anodic porous oxide region above the substrate; a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the first capacitor electrode region having a first wall perpendicular to the top surface; a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region, the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Inventors: Larry BUFFLE, Frédéric VOIRON, Julien EL SABAHY, Brigitte SOULIER
  • Publication number: 20230197440
    Abstract: An electrical device that includes: a metal barrier layer; an anodic porous oxide region on the metal barrier layer; a trench around the anodic porous oxide region reaching the metal barrier layer; a liner at least on a wall of the trench on a side of the anodic porous oxide region forming an electrical isolation barrier and having an opening onto the anodic porous oxide region; a hard mask arranged above the trenches and the liner having an opening onto the anodic porous oxide region. A corresponding manufacturing method is also disclosed.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 22, 2023
    Inventors: Brigitte SOULIER, Frédéric VOIRON
  • Publication number: 20230187143
    Abstract: A method for manufacturing an electrical device that includes: anodizing a portion of an anodizable metal layer so as to obtain an anodic porous oxide region and an anodizable metal region adjoining the anodic porous oxide region, the anodic porous oxide region being thicker than the anodizable metal region; depositing a layer of liner material on the anodic porous oxide region and on the anodizable metal region; depositing a layer of filler material on the layer of liner material to obtain a stacked structure having a top surface; planarizing the stacked structure from a top surface thereof until reaching the layer of the liner material, so as to expose a portion of liner material located above at least a portion of the anodic porous oxide region; and removing the exposed portion of liner material.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 15, 2023
    Inventors: Brigitte SOULIER, Frédéric VOIRON, Jullen EL SABAHY
  • Patent number: 11605759
    Abstract: An optoelectronic device including a substrate having opposite first and second surfaces; insulation trenches extending through the substrate, surrounding portions of the substrate and electrically insulating the portions from each other, each insulation trench being filled with at least one electrically insulating block and a gaseous volume or being filled with an electrically conductive element electrically isolated from the substrate; at least one light-emitting diode resting on the first surface for each portion of the substrate, the light-emitting diodes comprising wired, conical, or frustoconical semiconductor elements; an electrode layer covering at least one of the light-emitting diodes and a conductive layer overlying the electrode layer around the light-emitting diodes; and a layer encapsulating the light-emitting diodes and covering the entire first surface.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 14, 2023
    Assignees: Aledia, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Vincent Beix, Thomas Lacave, Marion Volpert, Olivier Girard, Denis Renaud, Brigitte Soulier
  • Publication number: 20220352024
    Abstract: A method of fabricating a semiconductor structure that includes: forming a first metal layer over a wafer; forming a second metal layer over the first metal layer; forming a first porous structure in a first region of the second metal layer located above a circuit area of the wafer and a second porous structure in a second region of the second metal layer located above a dicing area of the wafer, wherein the first porous structure includes a first set of pores, and wherein the second porous structure includes a second set of pores; forming a metal-insulator-metal stack in the first set of pores of the first porous structure; and etching the second set of pores of the second porous structure to expose the dicing area of the silicon wafer.
    Type: Application
    Filed: July 6, 2022
    Publication date: November 3, 2022
    Inventors: Frédéric VOIRON, Brigitte SOULIER, Hiroshi NAKAGAWA
  • Patent number: 11398579
    Abstract: A method for producing optoelectronic devices, including the following successive steps: providing a substrate having a first face; on the first face, forming sets of light-emitting diodes including wire-like, conical or frustoconical semiconductor elements; covering all of the first face with a layer encapsulating the light-emitting diodes; forming a conductive element that is insulated from the substrate and extends through the substrate from the second face to at least the first face; reducing the thickness of the substrate; and cutting the resulting structure in order to separate each set of light-emitting diodes.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 26, 2022
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Aledia
    Inventors: Christophe Bouvier, Emilie Pougeoise, Xavier Hugon, Carlo Cagli, Tiphaine Dupont, Philippe Gibert, Nacer Aitmani, Vincent Beix, Thomas Lacave, Marion Volpert, Olivier Girard, Denis Renaud, Brigitte Soulier
  • Publication number: 20210332492
    Abstract: A structure that includes: an insulating layer; a first metal layer above a first portion of the insulating layer; a first porous region of anodic oxide, above and in contact with the first metal layer; and a second porous region of anodic oxide, surrounding the first porous region, in contact with a second portion of the insulating layer adjacent to the first portion of the insulating layer, and in contact with the first metal layer, the second porous region forming an insulating region.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 28, 2021
    Inventors: Frédéric Voiron, Brigitte Soulier, Guy Parat
  • Publication number: 20210257514
    Abstract: An optoelectronic device including a substrate having opposite first and second surfaces; insulation trenches extending through the substrate, surrounding portions of the substrate and electrically insulating the portions from each other, each insulation trench being filled with at least one electrically insulating block and a gaseous volume or being filled with an electrically conductive element electrically isolated from the substrate; at least one light-emitting diode resting on the first surface for each portion of the substrate, the light-emitting diodes comprising wired, conical, or frustoconical semiconductor elements; an electrode layer covering at least one of the light-emitting diodes and a conductive layer overlying the electrode layer around the light-emitting diodes; and a layer encapsulating the light-emitting diodes and covering the entire first surface.
    Type: Application
    Filed: June 18, 2019
    Publication date: August 19, 2021
    Applicants: Aledia, Commissariat à I'Énergie Atomique et aux Énergies Alternatives
    Inventors: Vincent Beix, Thomas Lacave, Marion Volpert, Olivier Girard, Denis Renaud, Brigitte Soulier
  • Publication number: 20210028056
    Abstract: An electronic circuit including a semiconductor substrate having first and second opposite surfaces and electric insulation trenches. Each trench separates first and second portions of the substrate and includes electrically-insulating walls made of a first electrically-insulating material, extending from the first surface to the second surface, and a core made of a filling material, separated from the substrate by the walls. For at least one of the trenches, the trench walls include electrically-insulating portions made of the first electrically-insulating material protruding from the first or second surface outside of the substrate and/or the trench includes an electrically-insulating wall made of the first electrical-insulating material protruding from the first or second surface outside of the substrate and coupling the trench walls.
    Type: Application
    Filed: September 12, 2018
    Publication date: January 28, 2021
    Applicants: Commissariat à I'Énergie Atomique et aux Énergies Alternatives, Aledia
    Inventors: Adrien Gasse, Vincent Beix, Sylvie Jaryayes, Brigitte Soulier, Marion Volpert
  • Patent number: 10593588
    Abstract: An electronic circuit including a semiconducting or conducting substrate having first and second opposite surfaces and at least first and second non-parallel electrically insulating trenches that extend from the first surface in the substrate, define at least one portion of the substrate and join at a junction, the portion of the substrate including a protrusion that extends to the junction.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 17, 2020
    Assignees: Aledia, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Fabienne Goutaudier, Thomas Lacave, Vincent Beix, Stephan Borel, Bertrand Chambion, Brigitte Soulier
  • Publication number: 20180366365
    Abstract: An electronic circuit including a semiconducting or conducting substrate having first and second opposite surfaces and at least first and second non-parallel electrically insulating trenches that extend from the first surface in the substrate, define at least one portion of the substrate and join at a junction, the portion of the substrate including a protrusion that extends to the junction.
    Type: Application
    Filed: December 21, 2016
    Publication date: December 20, 2018
    Applicants: Aledia, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Fabienne Goutaudier, Thomas Lacave, Vincent Beix, Stephan Borel, Bertrand Chambion, Brigitte Soulier
  • Publication number: 20180301594
    Abstract: A method for producing optoelectronic devices, including the following successive steps: providing a substrate having a first face; on the first face, forming sets of light-emitting diodes including wire-like, conical or frustoconical semiconductor elements; covering all of the first face with a layer encapsulating the light-emitting diodes; forming a conductive element that is insulated from the substrate and extends through the substrate from the second face to at least the first face; reducing the thickness of the substrate; and cutting the resulting structure in order to separate each set of light-emitting diodes.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 18, 2018
    Applicants: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Aledia
    Inventors: Christophe Bouvier, Emilie Pougeoise, Xavier Hugon, Carolo Cagli, Tiphaine Dupont, Philippe Gibert, Nacer Aitmani, Vincent Beix, Thomas Lacave, Marion Volpert, Olivier Girard, Denis Renaud, Brigitte Soulier
  • Patent number: 8420500
    Abstract: The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: April 16, 2013
    Assignee: Soitec
    Inventors: Brigitte Soulier-Bouchet, Sébastien Kerdiles, Walter Schwarzenbach
  • Publication number: 20100304507
    Abstract: The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm.
    Type: Application
    Filed: September 11, 2008
    Publication date: December 2, 2010
    Applicant: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Brigitte Soulier Bouchet, Sébastien Kerdiles, Walter Schwarzenbach