Abstract: A networking device (810) includes user interface circuitry (838) operable for user input and display, a host processor (880) coupled with the user interface circuits (838); a network modem (870) and a peripheral interface processor (810) coupled with the host processor (880) and operable to automatically execute content receptions and transmission through the network modem (870) at least sometimes independently of the user interface circuits (838) and the host processor (880); and a local content storage (820) coupled with the peripheral interface processor (810) and wherein the peripheral interface processor (810) is operable with the modem (870) to transmit trigger signals representing controls to pull remote content from elsewhere and to subsequently receive such content via the modem (870) for the local content storage (820). Other network circuits, devices, systems and processes and peripheral interface circuits, devices, systems and processes are also disclosed.

Abstract: A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a single first in first out (FIFO) buffer in each serial channel is described. The RapidIO® data channel, for example, operates using a clock recovered from the data stream. The RapidIO® data stream has embedded special characters, where a select sequence of embedded characters is a clock compensation pattern. A look ahead circuit is used to detect the clock compensation pattern early and generate a clock compensation indicator signal. The FIFO writes data and the associated clock compensation indicator signal in a clock compensation indicator bit in synchronism with the recovered clock. A read circuit using a second clock of a different frequency than the first clock reads data and clock compensation bits from the FIFO and generates an almost empty signal when appropriate. A multiplexer is used at the FIFO output to pad data to the system interface.

Abstract: A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a first in first out (FIFO) buffer in each serial channel is described. A look ahead circuit is used to detect a clock compensation pattern early and generate a clock compensation indicator signal. Data and the clock compensation indicator signal are written in the FIFO in synchronism with the recovered clock. A read circuit using a second clock of a different frequency than the recovered clock reads data and clock compensation bits from the FIFO and generates an almost empty signal when appropriate. A multiplexer is used at the FIFO output to pad data to the system interface. A clock compensation control circuit generates a selection signal based on the almost empty signal and the clock compensation indicator bit read out of the FIFO to control the multiplexer selection signal.