Abstract: A method and system for providing on-product clocks for domains compatible with compression is disclosed. According to one embodiment, a base signal received from automated test equipment has a frequency for testing a plurality of clock domains and programming instruction for first and second clock domains of a plurality of clock domains. First and second clock signals are generated from the base clock signal based on the programming instruction. A first delay for the first clock signal and a second delay for the second clock signal are determined from the programming instruction. A test sequence is provided to test a first clock domain and a second clock domain. The test sequence comprises the first clock signal delayed by the first delay and the second clock signal delayed by the second delay. The first clock drives the first clock domain and the second clock derives the second clock domain.

Abstract: SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.

Abstract: A method and system for reducing switching activity of a spreader network during a scan-load operation is disclosed. According to one embodiment, a spreader network receives a plurality of scan input signals from a tester. A linear feedback shift register of the spread network is updated using the plurality of scan input signals. Each bit of the linear feedback shift register is shifted at each shift cycle for a plurality of shift cycles. The linear feedback shift register outputs a nonlinear gating signal using a first set of outputs and a data value feeding one or more scan chains of the spreader network using a second set of outputs. The pipeline clock of a pipeline element of the scan chains is gated using the nonlinear gating signal, and the data value is fed to the scan chains based on the pipeline clock. The scan chains are fed with updated values at the pipeline stage.

Abstract: A method and system for providing on-product clocks for domains compatible with compression is disclosed. According to one embodiment, a base signal received from automated test equipment has a frequency for testing a plurality of clock domains and programming instruction for first and second clock domains of a plurality of clock domains. First and second clock signals are generated from the base clock signal based on the programming instruction. A first delay for the first clock signal and a second delay for the second clock signal are determined from the programming instruction. A test sequence is provided to test a first clock domain and a second clock domain. The test sequence comprises the first clock signal delayed by the first delay and the second clock signal delayed by the second delay. The first clock drives the first clock domain and the second clock derives the second clock domain.

Abstract: During testing of an integrated circuit (IC), a channel masking capability is used for masking out unknown or unpredictable (X) values from being compressed into a signature register. The approach provides flexibility to allow for masking of unknown values, while avoiding many of the problems caused by over-masking of known values. The circuitry added to the design to allow for masking is reasonably small, and provides an effective way of masking unknown values during the testing process.

Abstract: A logic failure diagnosis system for performing logic failure diagnosis and methods for manufacturing and using same. The logic failure diagnosis system includes a signature register system and a space compaction system and, during testing, receives data values from a predetermined number of scan chains. During each scan cycle, the signature register system combines a set of data values with a set of recirculated data values to provide a set of data signature values. The signature register system recirculates the data signature values from the preceding scan cycle to provide the recirculated data values. The space compaction system compresses the data signature values to provide a compressed scan chain signature for the scan chains. The compressed scan chain signature can be compared with a set of expected values to determine whether the scan chains include any erroneous values and, if so, to identify a source of the erroneous values.

Abstract: An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits.

Abstract: A logic failure diagnosis system for performing logic failure diagnosis and methods for manufacturing and using same. The logic failure diagnosis system includes a signature register system and a space compaction system and, during testing, receives data values from a predetermined number of scan chains. During each scan cycle, the signature register system combines a set of data values with a set of recirculated data values to provide a set of data signature values. The signature register system recirculates the data signature values from the preceding scan cycle to provide the recirculated data values. The space compaction system compresses the data signature values to provide a compressed scan chain signature for the scan chains. The compressed scan chain signature can be compared with a set of expected values to determine whether the scan chains include any erroneous values and, if so, to identify a source of the erroneous values.

Abstract: A method and apparatus for improving the efficiency of scan testing of integrated circuits is described. This efficiency is achieved by reducing the amount of required test stimulus source data and by increasing the effective bandwidth of the scan-load operation. The reduced test data volume and corresponding test time are achieved by integrating a real-time test data decoder or logic network into each integrated circuit chip.