Abstract: A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.

Abstract: A transistor device includes a first trench and a second trench arranged in a comb-like structure, first sections of the first and second trenches corresponding to teeth of the comb-like structure and second sections of the first and second trenches corresponding to opposing shafts of the comb-like structure. The arrangement of the first trench and the second trench forms a pattern of interdigitated fingers. Transistor cells of the transistor device are disposed between single fingers of the first and second trenches. A semiconductor mesa separates the first trench and the second trench from each other. A gate electrode in the first trench or a gate electrode in the second trench is electrically connected to a source potential instead of a gate potential to decrease a gate charge of the transistor device.

Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.

Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.

Abstract: A transistor device includes a first trench and a second trench arranged in a comb-like structure, first sections of the first and second trenches corresponding to teeth of the comb-like structure and second sections of the first and second trenches corresponding to opposing shafts of the comb-like structure. The arrangement of the first trench and the second trench forms a pattern of interdigitated fingers. Transistor cells of the transistor device are disposed between single fingers of the first and second trenches. A semiconductor mesa separates the first trench and the second trench from each other. A gate electrode in the first trench or a gate electrode in the second trench is electrically connected to a source potential instead of a gate potential to decrease a gate charge of the transistor device.

Abstract: A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.

Abstract: A semiconductor device includes a first trench and a second trench in a first main surface of a semiconductor substrate. Each of the first and second trenches includes first sections extending lengthwise in a first direction and a second section extending lengthwise in a second direction transvers to the first direction, the second section of the first trench being disposed opposite to the second section of the second trench. The semiconductor device further includes a semiconductor mesa separating the first and second trenches, and a source metal layer above the first main surface of the semiconductor substrate and electrically connected to source regions in the semiconductor mesa. Corresponding methods of manufacture are also described.

Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.

Abstract: A semiconductor device includes a plurality of striped-shaped trenches extending into a semiconductor substrate. At least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches. A gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches. Trench insulation material is located in each trench of the first group of trenches. A thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches.

Abstract: A semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body. The trench has a stripe configuration and extends laterally within the active region. A first electrode and a first insulator are in the trench. The first insulator insulates the first electrode from the semiconductor body. The first electrode is recessed in the trench and has a planar surface extending generally parallel with and below the main surface of the semiconductor body so as to define a well in the trench that is laterally confined by the first insulator. A second insulator is on the planar surface. A second electrode is within the well of the trench, and the second insulator insulates the second electrode from the first electrode.

Abstract: A semiconductor device includes a first trench and a second trench in a first main surface of a semiconductor substrate. Each of the first and second trenches includes first sections extending lengthwise in a first direction and a second section extending lengthwise in a second direction transvers to the first direction, the second section of the first trench being disposed opposite to the second section of the second trench. The semiconductor device further includes a semiconductor mesa separating the first and second trenches, and a source metal layer above the first main surface of the semiconductor substrate and electrically connected to source regions in the semiconductor mesa. Corresponding methods of manufacture are also described.

Abstract: A semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body. The trench has a stripe configuration and extends laterally within the active region. A first electrode and a first insulator are in the trench. The first insulator insulates the first electrode from the semiconductor body. The first electrode is recessed in the trench and has a planar surface extending generally parallel with and below the main surface of the semiconductor body so as to define a well in the trench that is laterally confined by the first insulator. A second insulator is on the planar surface. A second electrode is within the well of the trench, and the second insulator insulates the second electrode from the first electrode.

Abstract: A semiconductor device includes a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa is arranged between the first gate trench and the second gate trench. The mesa separates the first gate trench from the second gate trench. Each of the first and second gate trenches includes first sections extending in a first direction and second sections connecting adjacent ones of the first sections. The second sections of the first gate trench are disposed opposite to the second sections of the second gate trench with respect to a plane perpendicular to the first direction.

Abstract: A method of processing a semiconductor device is presented. The method includes providing a semiconductor body; forming a trench within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body; forming, within the trench, a first electrode and a first insulator insulating the first electrode from the semiconductor body; carrying out a first etching step for partially removing the first electrode along the total lateral extension of the first electrode such that the remaining part of the first electrode has a planar surface, thereby creating a well in the trench that is laterally confined by the first insulator; depositing a second insulator on top the planar surface; and forming a second electrode within the well of the trench. The second insulator insulates the second electrode from the first electrode.

Abstract: A semiconductor device includes a plurality of striped-shaped trenches extending into a semiconductor substrate. At least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches. A gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches. Trench insulation material is located in each trench of the first group of trenches. A thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches.

Abstract: A method of processing a semiconductor device includes: creating first and second recesses in a surface of a semiconductor body; creating an insulation layer that forms first and second wells each having a common lateral extension range with the portion of the insulation layer located between the recesses; filling the wells with a plug material having the respective common lateral extension range with the insulation layer; removing a middle portion of the insulation layer located between the recesses; filling, with a filling material, a third recess created in a region where the middle portion has been removed and at least a portion of the space located between the wells; creating a first common surface of the insulation layer, the plug material, and the filling material; removing the plug material from the second well; and creating a second insulation layer that covers a side wall of the second recess.

Abstract: A method of processing a semiconductor device is presented. The method includes providing a semiconductor body; forming a trench within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body; forming, within the trench, a first electrode and a first insulator insulating the first electrode from the semiconductor body; carrying out a first etching step for partially removing the first electrode along the total lateral extension of the first electrode such that the remaining part of the first electrode has a planar surface, thereby creating a well in the trench that is laterally confined by the first insulator; depositing a second insulator on top the planar surface; and forming a second electrode within the well of the trench. The second insulator insulates the second electrode from the first electrode.

Abstract: A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.

Abstract: A semiconductor device includes a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa is arranged between the first gate trench and the second gate trench. The mesa separates the first gate trench from the second gate trench. Each of the first and second gate trenches includes first sections extending in a first direction and second sections connecting adjacent ones of the first sections. The second sections of the first gate trench are disposed opposite to the second sections of the second gate trench with respect to a plane perpendicular to the first direction.