Patents by Inventor Brittany L. Hedrick

Brittany L. Hedrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10090255
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and methods of manufacture. The structure includes: one or more redistribution layers; a glass interposer connected to the one or more redistribution layers; a channel formed through the one or more redistribution layers and the glass interposer core, forming a dicing channel; and polymer material conformally filling the channel.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brittany L. Hedrick, Vijay Sukumaran, Christopher L. Tessler, Richard F. Indyk, Sarah H. Knickerbocker
  • Patent number: 10049909
    Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick, Edmund J. Sprogis
  • Publication number: 20180082965
    Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 22, 2018
    Applicant: SUSS MicroTec Photonic Systems Inc.
    Inventors: Brian M. Erwin, Brittany L. Hedrick, Nicholas A. Polomoff, TaeHo Kim, Matthew E. Souter
  • Publication number: 20180076160
    Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Applicant: SUSS MicroTec Photonic Systems Inc.
    Inventors: Brian M. Erwin, Brittany L. Hedrick, Nicholas A. Polomoff, TaeHo Kim, Matthew E. Souter
  • Publication number: 20170221837
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and methods of manufacture. The structure includes: one or more redistribution layers; a glass interposer connected to the one or more redistribution layers; a channel formed through the one or more redistribution layers and the glass interposer core, forming a dicing channel; and polymer material conformally filling the channel.
    Type: Application
    Filed: January 29, 2016
    Publication date: August 3, 2017
    Inventors: Brittany L. Hedrick, Vijay Sukumaran, Christopher L. Tessler, Richard F. Indyk, Sarah H. Knickerbocker
  • Publication number: 20170154800
    Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.
    Type: Application
    Filed: February 14, 2017
    Publication date: June 1, 2017
    Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. HEDRICK, Edmund J. Sprogis
  • Publication number: 20170117241
    Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Applicant: SUSS MicroTec Photonic Systems Inc.
    Inventors: Brian M. Erwin, Brittany L. Hedrick, Nicholas A. Polomoff, TaeHo Kim, Matthew E. Souter
  • Patent number: 9613842
    Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick, Edmund J. Sprogis
  • Publication number: 20150235891
    Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 20, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick, Edmund J. Sprogis