Abstract: The present innovation is directed to a single-chip integrated circuit power amplifier configured to employ the efficiency enhancement techniques utilized in Doherty amplifiers. The single-chip integrated circuit power amplifier may be implemented using uniquely designed biasing circuits as described herein. Also, the use of combined HBT/FET processes and a lumped quarter-wavelength transformer may be inherently well suited for the implementation of Doherty amplifiers in the single-chip techniques described herein.

Abstract: The present innovation is directed to a single-chip integrated circuit power amplifier configured to employ the efficiency enhancement techniques utilized in Doherty amplifiers. The single-chip integrated circuit power amplifier may be implemented using uniquely designed biasing circuits as described herein. Also, the use of combined HBT/FET processes and a lumped quarter-wavelength transformer may be inherently well suited for the implementation of Doherty amplifiers in the single-chip techniques described herein.

Abstract: A method of determining the accuracy error in scanning signals of a semiconductor line width metrology device comprises the steps of creating a frequency signature template of a patterned feature formed on a semiconductor layer with a line width metrology measurement device that is in nominal operating condition. Another patterned feature similar to the first patterned feature is scanned and the waveform signal is generated of the line width patterned feature. The waveform signal is processed and converted into a frequency signature which is compared with the frequency signature template.

Abstract: A method of analyzing a patterned feature formed on a semiconductor layer is disclosed. The patterned feature is scanned to generate an amplitude modulated waveform signal of the line width. This waveform signal is processed for calculating the scale and shape of the patterned feature based on the profile of the amplitude modulated waveform signal. The calculated scale and shape of the patterned feature are compared to a template of a normal patterned feature having the desired shape and scale. The template is derived from scanning a normal patterned feature on a known sample.

Abstract: A non-destructive method for evaluating a topographical feature 16 of an integrated circuit 42, such as a photoresist runner, includes core sectioning the feature to remove a small section 22, without damage to the remainder of the wafer 36 on which the integrated circuit is formed. A tool having fine adjustment, such as a micromanipulator with a rod-shaped probe 24 in the form of a glass needle, is used to remove the section for examination and metrology. The section is separated from the underlying substrate surface 14 and can be examined from all sides. Variations in a critical dimension, such as line width W, along the length L of the section, as well as average measurements of the dimension, can be obtained.

Abstract: A method for analyzing a semiconductor surface having patterned features on the surface is disclosed. At least one patterned feature is scanned to produce a scanned waveform signal having signal segments corresponding to characteristic surface portions of the patterned feature. The signal segments are processed using an auto-correlation function to produce an auto-correlation signal for each characteristic surface portion of the patterned feature. A reference signal having signal segments corresponding to characteristic surface portions of a known patterned feature is provided and each segment of the auto-correlation signal is compared to the respective signal segments of the reference signal.

Abstract: A method for amplifying defects connected to a top surface of a semiconductor device comprises the steps of applying a dye, removing the dye, and applying a developing gel. The dye enters into defects connected to the top surface of the semiconductor device. After removal of the dye from the top surface and application of the developing gel, the dye contained within the defects leaches into the developing gel to form defect indications. These defect indications have a better optical visibility than the defects themselves. An apparatus for performing this method is also disclosed.