Abstract: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: An integrated circuit device comprising an integrated circuit die mounted on a leadframe having a plurality of inner leads. The integrated circuit die has a plurality of bond pads that are electrically connected to the inner leads of the leadframe, wherein at least two bond pads are connected to a one of the plurality of inner leads and/or at least two inner leads are connected to one or more bond pads with a single bond wire. A single bond wire is connected to a first bond pad or inner lead and subsequently wedge or stitch bonded to a second bond pad or inner lead, then it is connected to a third bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and inner lead(s). The bond pad(s) of the die and inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: An integrated circuit device comprising an integrated circuit die mounted on a leadframe having a plurality of inner leads. The integrated circuit die has a plurality of bond pads that are electrically connected to the inner leads of the leadframe, wherein at least two bond pads are connected to a one of the plurality of inner leads and/or at least two inner leads are connected to one or more bond pads with a single bond wire. A single bond wire is connected to a first bond pad or inner lead and subsequently wedge or stitch bonded to a second bond pad or inner lead, then it is connected to a third bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and inner lead(s). The bond pad(s) of the die and inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: An EEPROM having reduced circuit loading of a high voltage write pulse by dividing an array of bit cells into two or more switchable common source segments. Only common source segments containing the bit cells being written to are connected, the other common source segments remain unconnected and do not contribute substantially to loading of the write pulse. Having multiple switchable common segmentations reduces the amount of parasitic capacitance connected in the EEPROM array during a write operation, thus reducing loading on the write circuits. Also reducing the number of bit cells having the common source segments connected during a write operation reduces the amount of leakage current contribution which adversely affects the write operation.

Abstract: An EEPROM having reduced circuit loading of a high voltage write pulse by dividing an array of bit cells into two or more switchable common source segments. Only common source segments containing the bit cells being written to are connected, the other common source segments remain unconnected and do not contribute substantially to loading of the write pulse. Having multiple switchable common segmentations reduces the amount of parasitic capacitance connected in the EEPROM array during a write operation, thus reducing loading on the write circuits. Also reducing the number of bit cells having the common source segments connected during a write operation reduces the amount of leakage current contribution which adversely affects the write operation.

Abstract: An adaptive digital squelch system, responsive to ambient RF background noise, that automatically adjusts the receiver squelch level during intervals when no valid signal is being received. A valid signal is considered to be a signal that is greater than the receiver squelch level and which contains an audio signal at a specific frequency; otherwise, the signal is considered noise. When the invention detects the absence of a valid signal, the squelch level is periodically calculated by averaging multiple noise signal levels at multiple frequencies.

Abstract: A frequency hopping spread spectrum receiver that does not require an independent synchronization source to receive and track a frequency hopping transmitter signal. In a search mode, the receiver of this invention hops in a reverse direction and at a faster rate than the transmitter hopping pattern. This results in faster signal acquisition time. The receiver uses the audio data tones of the transmit signal to detect and synchronize to the transmitter signal. Once in track mode of operation, a frequency hopping hysteresis ensures against erroneous detection of signal loss by tracking the transmitter hopping pattern for several consecutive hops before switching back to search mode.

Abstract: A beacon system wherein a beacon station is placed at a landmark such as a state line adjacent a major highway to broadcast information-containing alternating directional signals. In addition, each vehicle may be equipped with a radio receiver, a receiving decoder and a data analysis processor for receiving data signals from the beacon station. The beacon station includes an information encoder for generating first and second alternating but distinct location signals, first and second directional antennas disposed to radiate in opposite directions along the path of travel, the directional antennas having a significant back attenuation, a radio frequency transmitter for broadcasting the two location signals, preferably as data packets, to vehicle-mounted receivers along the path of travel, and an r.f. switcher for switching signal output of the transmitter between the two antennas in synchronization with the two location signals.