Abstract: A fuzzy alphanumeric search apparatus searches for a search character string (e.g., MPN) in a source character string (CPN) database. The match is fuzzy since it only matches some of the MPN characters (referred to as tokens) against some of the CPN characters. Nearly all part numbers have a base number (base token) that is typically found at the beginning of the MPN. A base token and other tokens are generated, used to identify CPNs having the greatest total of MPN character position matches, and are outputted as a potential (fuzzy) CPN match list to the user. The user then determines if in fact a true CPN match is found in the fuzzy CPN list. The Fuzzy MPN match technique is significantly faster than manual wildcard searches.

Abstract: A semiconductor accelerometer is formed by attaching a semiconductor layer to a handle wafer by a thick oxide layer. Accelerometer geometry is patterned in the semiconductor layer, which is then used as a mask to etch out a cavity in the underlying thick oxide. The mask may include one or more apertures, so that a mass region will have corresponding apertures to the underlying oxide layer. The structure resulting from an oxide etch has the intended accelerometer geometry of a large volume mass region supported in cantilever fashion by a plurality of piezo-resistive arm regions to a surrounding, supporting portion of the semiconductor layer. Directly beneath this accelerometer geometry is a flex-accommodating cavity realized by the removal of the underlying oxide layer.

Abstract: Integrated circuits are fabricated on a bonded wafer which has a buried silicide layer.

Abstract: A chamber, e.g., an oven, has open access ports through a wall thereof opening into the chamber. Cooperating with the access ports are a number of mounting assemblies each comprising a front section, for disposition within the chamber via the access port, and a rear section for extending exteriorly of the chamber. Device receiving sockets are mounted on the front section and electrical plug receiving sockets are mounted on the rear section. The front and rear sockets are electrically wired together for applying electrical power to the devices on the front section. An intermediate member is disposed between the front and rear sections providing thermal isolation therebetween and providing means for sealing the access ports when a mounting assembly is disposed therethrough. Variable socket to socket wiring means are also provided.

Abstract: VMOS transistors are formed with gate segments in dielectric trenches separating islands formed on a common dielectric base. A trench gate may be common for VMOS at opposed edges of adjacent islands, for VMOS at common edge of common islands or for VMOSs at uncommon edges of common islands. Common regions of an island may be used to form parallel or series VMOS with separate trench gates. The trenches may be formed after device region formation. Isolated gate segments may be formed by removing portions of dielectrically filled trenches to form recesses to be filled with gate material or forming gate material filled dielectric trenches and removing portions of the gate material and refilling with dielectric to form the isolated gate segments.

Abstract: VMOS transistors are formed with gate segments in dielectric trenches separating islands formed on a common dielectric base. A trench gate may be common for VMOS at opposed edges of adjacent islands, for VMOS at common edge of common islands or for VMOSs at uncommon edges of common islands. Common regions of an island may be used to form parallel or series VMOS with separate trench gates. The trenches may be formed after device region formation. Isolated gate segments may be formed by removing portions of dielectrically filled trenches to form recesses to be filled with gate material or forming gate material filled dielectric trenches and removing portions of the gate material and refilling with dielectric to form the isolated gate segments.

Abstract: A method includes forming an oxide layer on the substrate of a first thickness and patterning the insulative layer to form the laterally dielectric walls in exposed island areas of the substrate. The islands are epitaxially grown on the exposed surface of the substrate to a second thickness to form the laterally dielectrically isolated islands. For totally dielectrically isolated islands, the second thickness is less than the first thickness and a horizontal dielectric isolation is formed in the epitaxial layer by ion implanting oxygen. This is followed by increasing the island thickness to the first thickness by further epitaxial growth.

Abstract: A process for manufacturing an insulated gate field effect semiconductor device having self-aligned contact regions. The process avoids the need for a masking step for the application of interconnecting contacts by providing a dielectric material having a low melting point over the gate region of the semiconductor. The dielectric material is heated to its melting point such that it covers and encapsulates the gate. Contact material is then subsequently provided using the self-alignment feature of the melted dielectric which isolates the gate from the contacts.

Abstract: A process for manufacturing a bipolar semiconductor device having self-aligned contact regions. The process avoids the need for a masking step for the application of interconnecting contacts by providing a dielectric material having a low melting point over the emitter region of the semiconductor. The dielectric material is heated to its melting point such that it covers and encapsulates the emitter. Conductive contact material is then subsequently provided using the self-alignment feature of the melted dielectric which isolates the base from the contacts.