Abstract: Disclosed is a high data integrity processing system (“HDIPS”) that includes a first processing device and a triple voted processing (“TVP”) device in signal communication with the first processing device. The first processing device has a high radiation resistance and includes a processor, a cache memory, and a computer-readable medium (“CRM”). The CRM has encoded thereon computer-executable instructions to cause the processer to execute a periodic first integrity check on the first processing device producing a first integrity result, which is transmitted to the TVP device. The TVP device includes firmware having encoded thereon machine instructions to, simultaneously with the periodic first integrity check, cause the TVP device to execute a second integrity check producing a second integrity result, compare the first integrity result with the second integrity result, and power reset the first processing device if the first integrity result does not match the second integrity result.

Abstract: Disclosed is a high data integrity processing system (“HDIPS”) that includes a first processing device and a triple voted processing (“TVP”) device in signal communication with the first processing device. The first processing device has a high radiation resistance and includes a processor, a cache memory, and a computer-readable medium (“CRM”). The CRM has encoded thereon computer-executable instructions to cause the processer to execute a periodic first integrity check on the first processing device producing a first integrity result, which is transmitted to the TVP device. The TVP device includes firmware having encoded thereon machine instructions to, simultaneously with the periodic first integrity check, cause the TVP device to execute a second integrity check producing a second integrity result, compare the first integrity result with the second integrity result, and power reset the first processing device if the first integrity result does not match the second integrity result.