Patents by Inventor Bruce A. Dickey

Bruce A. Dickey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Microsequencer with nested loop counters
    Patent number: 6968448
    Abstract: A pattern generator includes an address generator, an address topology generator, and a data topology generator. The address generator is adapted to provide a first address having a plurality of address bits. The address topology generator includes a first plurality of programmable logic gates. Each programmable logic gate of the first plurality is coupled to receive at least a subset of the plurality of address bits. The first plurality of programmable logic gates generate a second address having a plurality of modified address bits. The data topology generator is adapted to receive at least a subset of the plurality of modified address bits and generate write data based on the subset of modified address bits. A method for generating a pattern includes generating a first address having a plurality of address bits. A second address having a plurality of modified address bits is generated. The second address is a programmable combination of subsets of the address bits.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: November 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Charles K. Snodgrass, Bruce A. Dickey
  • Microsequencer with nested loop counters
    Publication number: 20010054141
    Abstract: A pattern generator includes an address generator, an address topology generator, and a data topology generator. The address generator is adapted to provide a first address having a plurality of address bits. The address topology generator includes a first plurality of programmable logic gates. Each programmable logic gate of the first plurality is coupled to receive at least a subset of the plurality of address bits. The first plurality of programmable logic gates generate a second address having a plurality of modified address bits. The data topology generator is adapted to receive at least a subset of the plurality of modified address bits and generate write data based on the subset of modified address bits. A method for generating a pattern includes generating a first address having a plurality of address bits. A second address having a plurality of modified address bits is generated. The second address is a programmable combination of subsets of the address bits.
    Type: Application
    Filed: July 24, 2001
    Publication date: December 20, 2001
    Applicant: Micron Technology, Inc.
    Inventors: Charles K. Snodgrass, Bruce A. Dickey
  • Programmable pattern generator
    Patent number: 6321356
    Abstract: A pattern generator includes an address generator, an address topology generator, and a data topology generator. The address generator is adapted to provide a first address having a plurality of address bits. The address topology generator includes a first plurality of programmable logic gates. Each programmable logic gate of the first plurality is coupled to receive at least a subset of the plurality of address bits. The first plurality of programmable logic gates generate a second address having a plurality of modified address bits. The data topology generator is adapted to receive at least a subset of the plurality of modified address bits and generate write data based on the subset of modified address bits. A method for generating a pattern includes generating a first address having a plurality of address bits. A second address having a plurality of modified address bits is generated. The second address is a programmable combination of subsets of the address bits.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: November 20, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Charles K. Snodgrass, Bruce A. Dickey