Patents by Inventor Bruce A. Doyle
Bruce A. Doyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240127145Abstract: A system for labor scheduling and jobsite management is disclosed that manages a dynamically changing workforce. The system includes a graphical user interface (GUI) and a processor circuit that controls the GUI. The system provides a plurality of user-selectable input screens that allow input of information regarding employee onboarding, flexible staffing and workflow management, time entry/payroll support, significant event reporting, and medical protocol management. The system receives user input from one or more of the user-selectable input screens and generates, and dynamically updates, a plurality of work schedules for a respective plurality of workers having different skills working on different aspects of a job at different times as the job progresses.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Inventors: Timothy Michael HOCH, Julie DOYLE, Bruce BEVER, Richard Jake LOCKLEAR, Dawn Lynn MANNING, Cindy Lee STATON
-
Patent number: 11824436Abstract: A detector circuit included in a computer system filters the voltage level of a power supply node to generate filtered signals. The detector circuit either compares the filtered signals or samples the filtered signal and compares the samples to reference levels to detect changes in the voltage level of the power supply node that exceed thresholds for magnitude and duration. A control circuit included in the computer system generates, using the glitch signal, control signals that can be used to change operating parameters of functional circuits included in the computer system.Type: GrantFiled: June 1, 2021Date of Patent: November 21, 2023Assignee: Apple Inc.Inventors: Xiao Pu, Bruce A. Doyle
-
Publication number: 20220385170Abstract: A detector circuit included in a computer system filters the voltage level of a power supply node to generate filtered signals. The detector circuit either compares the filtered signals or samples the filtered signal and compares the samples to reference levels to detect changes in the voltage level of the power supply node that exceed thresholds for magnitude and duration. A control circuit included in the computer system generates, using the glitch signal, control signals that can be used to change operating parameters of functional circuits included in the computer system.Type: ApplicationFiled: June 1, 2021Publication date: December 1, 2022Inventors: Xiao Pu, Bruce A. Doyle
-
Patent number: 8947967Abstract: Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.Type: GrantFiled: December 21, 2012Date of Patent: February 3, 2015Assignee: Advanced Micro Devices Inc.Inventors: Michael Dreesen, Stephen Greenwood, Bruce Doyle
-
Publication number: 20140177349Abstract: Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: Advanced Micro Devices Inc.Inventors: Michael DREESEN, Stephen GREENWOOD, Bruce DOYLE
-
Patent number: 8729944Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.Type: GrantFiled: December 21, 2011Date of Patent: May 20, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Bruce A. Doyle, Emerson S. Fang, Alvin L. Loke, Shawn Searles, Stephen F. Greenwood
-
Publication number: 20140049292Abstract: An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicants: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Petre Popescu, Emerson S. Fang, Bruce A. Doyle, Alvin Leng Sun Loke, Shawn Searles
-
Patent number: 8542068Abstract: A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.Type: GrantFiled: December 21, 2011Date of Patent: September 24, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Bruce A. Doyle, Emerson S. Fang, Alvin L. Loke, Shawn Searles, Stephen F. Greenwood
-
Publication number: 20130162310Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Bruce A. DOYLE, Emerson S. FANG, Alvin L. LOKE, Shawn SEARLES, Stephen F. GREENWOOD
-
Publication number: 20130162357Abstract: A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Bruce A. DOYLE, Emerson S. FANG, Alvin L. LOKE, Shawn SEARLES, Stephen F. GREENWOOD
-
Patent number: 8319579Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.Type: GrantFiled: November 29, 2010Date of Patent: November 27, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Jingcheng Zhuang, Bruce A. Doyle, Emerson S. Fang
-
Publication number: 20120133459Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.Type: ApplicationFiled: November 29, 2010Publication date: May 31, 2012Inventors: Jingcheng Zhuang, Bruce A. Doyle, Emerson S. Fang
-
Patent number: 7498858Abstract: Embodiments of an interpolator system and method are disclosed. One embodiment of an interpolator system, among others, includes an interpolator having first and second output terminals providing output signals; a comparator coupled to the first and second output terminals and configured to detect a peak voltage level of the output signals and compare the peak voltage level with a reference voltage level; and an impedance element coupled to the comparator and the first and second output terminals, wherein the comparator is configured to provide a control signal to the impedance element to change the impedance of the impedance element to set a voltage variation of the output signals.Type: GrantFiled: November 1, 2004Date of Patent: March 3, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jayen J. Desai, Bruce Doyle
-
Publication number: 20070229147Abstract: For one disclosed embodiment, a supply voltage regulator is to control voltage at a first supply node for a circuit. The supply voltage regulator includes one or more first devices to couple the first supply node to a second supply node when the circuit is in a predetermined operational state and includes an error sensor to control the one or more first devices. The supply voltage regulator includes one or more second devices to couple the first supply node to a third supply node when the circuit is in the predetermined operational state. Other embodiments are also disclosed.Type: ApplicationFiled: March 30, 2006Publication date: October 4, 2007Inventors: Bruce Doyle, Manish Kumar, John Wuu, Samuel Naffziger
-
Publication number: 20060265174Abstract: A thermal sensing system may comprise a plurality of remote sensors distributed across an integrated circuit (IC). Each of the plurality of remote sensors provides an analog signal that varies as a function of temperature of a respective region of the IC where each respective remote sensor is located. A central system, forming part of the IC, samples the analog signals from the plurality of remote sensors and converts the sampled analog signals to corresponding digital values.Type: ApplicationFiled: May 18, 2005Publication date: November 23, 2006Inventors: Bruce Doyle, Samuel Naffziger, Christopher Poirier, James Ignowski
-
Patent number: 7135892Abstract: Systems, methodologies, media and other embodiments associated with peak detectors are described. One exemplary system embodiment includes a voltage peak detector comprising a first detector logic configured to detect a peak voltage of an input signal. The first detector logic has a circuit behavior that produces a leakage current that may alter the peak voltage. The system can also include a second detector logic configured to replicate the circuit behavior of the first detector logic including being configured to produce a replica leakage current that is equivalent to the leakage current. The second detector logic can be operably connected to the first detector logic to cause the replica leakage current to negate the leakage current.Type: GrantFiled: June 29, 2004Date of Patent: November 14, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Bruce Doyle, Gregory L. Ranson
-
Publication number: 20060091925Abstract: Embodiments of an interpolator system and method are disclosed. One embodiment of an interpolator system, among others, includes an interpolator having first and second output terminals providing output signals; a comparator coupled to the first and second output terminals and configured to detect a peak voltage level of the output signals and compare the peak voltage level with a reference voltage level; and an impedance element coupled to the comparator and the first and second output terminals, wherein the comparator is configured to provide a control signal to the impedance element to change the impedance of the impedance element to set a voltage variation of the output signals.Type: ApplicationFiled: November 1, 2004Publication date: May 4, 2006Inventors: Jayen Desai, Bruce Doyle
-
Publication number: 20050285634Abstract: Systems, methodologies, media and other embodiments associated with peak detectors are described. One exemplary system embodiment includes a voltage peak detector comprising a first detector logic configured to detect a peak voltage of an input signal. The first detector logic has a circuit behavior that produces a leakage current that may alter the peak voltage. The system can also include a second detector logic configured to replicate the circuit behavior of the first detector logic including being configured to produce a replica leakage current that is equivalent to the leakage current. The second detector logic can be operably connected to the first detector logic to cause the replica leakage current to negate the leakage current.Type: ApplicationFiled: June 29, 2004Publication date: December 29, 2005Inventors: Bruce Doyle, Gregory Ranson
-
Patent number: 5546026Abstract: A sense amplifier circuit includes a voltage developing stage which receives first and second data inputs, din1 and din2, and generates a differential voltage, in response to feedback signals received from a first and second data outputs, dout1 and dour2, of the sense amplifier circuit, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a full-swing locking stage which generates and latches, in response to a control signal .PHI..sub.2 ', complementary latched data outputs from the first and second data outputs, dout1 and dout2, generated by the voltage developing stage; and a voltage equalization stage which equalizes, in response to a control signal .PHI..sub.0 ', voltages on data lines respectively connected to the first and second data outputs, dout1 and dout2. In addition, the voltage equalization stage is used to initiate the voltage developing stage. Timing of the control signals, .PHI..sub.0 ' and .PHI..sub.2 ', is such that the control signal .PHI..Type: GrantFiled: May 1, 1995Date of Patent: August 13, 1996Assignee: Cirrus Logic, Inc.Inventors: Jyhfong Lin, Bruce Doyle
-
Patent number: 5410311Abstract: There is disclosed a circuit and method for providing a reference voltage to a matrix array of video DAC cells. The circuit is located substantially within a center of the matrix array in order to minimize any effects upon the delivered reference voltage that process variations within the integrated circuit supporting the video DAC may produce. The center location minimizes the average distance between the voltage reference circuit and each of the DAC cells within the matrix array. In a preferred embodiment, the circuit is divided so that a reference voltage supplied by one portion of the circuit is unaffected by inherent capacitances within the MOSFET devices utilized within the circuit coupling that voltage reference to the other reference voltages supplied by the second portion of the circuit.Type: GrantFiled: July 29, 1993Date of Patent: April 25, 1995Assignee: Pixel Semiconductor, Inc.Inventor: Bruce A. Doyle