Abstract: A detector circuit included in a computer system filters the voltage level of a power supply node to generate filtered signals. The detector circuit either compares the filtered signals or samples the filtered signal and compares the samples to reference levels to detect changes in the voltage level of the power supply node that exceed thresholds for magnitude and duration. A control circuit included in the computer system generates, using the glitch signal, control signals that can be used to change operating parameters of functional circuits included in the computer system.

Abstract: A detector circuit included in a computer system filters the voltage level of a power supply node to generate filtered signals. The detector circuit either compares the filtered signals or samples the filtered signal and compares the samples to reference levels to detect changes in the voltage level of the power supply node that exceed thresholds for magnitude and duration. A control circuit included in the computer system generates, using the glitch signal, control signals that can be used to change operating parameters of functional circuits included in the computer system.

Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Abstract: An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.

Abstract: A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Abstract: A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

Abstract: There is disclosed a circuit and method for providing a reference voltage to a matrix array of video DAC cells. The circuit is located substantially within a center of the matrix array in order to minimize any effects upon the delivered reference voltage that process variations within the integrated circuit supporting the video DAC may produce. The center location minimizes the average distance between the voltage reference circuit and each of the DAC cells within the matrix array. In a preferred embodiment, the circuit is divided so that a reference voltage supplied by one portion of the circuit is unaffected by inherent capacitances within the MOSFET devices utilized within the circuit coupling that voltage reference to the other reference voltages supplied by the second portion of the circuit.

Abstract: A voltage level sense circuit that has temperature compensation is disclosed. The circuit includes charge-sharing capacitors in each of an input leg and a reference leg. The charge-sharing capacitors are precharged to voltages that are integral multiples of the forward bias voltage drop across the base-emitter junction of a bipolar transistor. The bipolar transistors in the input leg differ from those in the reference leg, so that the difference in base-emitter on voltages increases with temperature. The increasing difference in base-emitter on voltage compensates for the decrease in the absolute value of the base-emitter on voltage with temperature. Voltage level sensing is accomplished by sampling the input voltage with a capacitor, charge-sharing the sampled voltage with one of the precharged charge-sharing capacitors, and coupling the charge-shared result to an input of a differential amplifier comparator.

Abstract: An EEPROM cell suitable for use in programmable logic devices contains three transistors. A floating gate transistor is used to retain a programmed value using charge storage on the floating gate. A read transistor is connected between the floating gate transistor and an output signal line, and used to access the value stored in the floating gate transistor. A write transistor is connected to the floating gate transistor opposite the read transistor, and is used when programming the floating gate transistor. The write transistor and its associated control circuitry are fabricated to handle the higher programming voltages required by the floating gate device. The read transistor and associated drive circuitry are not required to handle the higher programming voltages, and can be fabricated using smaller, faster devices.

Abstract: A shift register used to shift programming and test data into a programmable logic device is modified so that each bit thereof can be directly set or reset. Control signals can be used to directly place the required test patterns into the shift register. A memory connected to the shift register, and associated logic, provides a means for testing whether data was accurately written to the array without shifting any data off of the device.

Abstract: A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.