Abstract: A conversion system which checks a word for exceptions; converts the word to phonemes utilizing sentence structure and word structure; and finally, converts the phonemes to LPC parameters. When an exception is found in the first stage the correct phonemes may be provided or an alternate spelling or set of rules may be used to provide the correct phonemes. The LPC parameters are then smoothed, to produce a continuous speech pattern, and then transmitted. This results in the conversion of a computer network signal to a voice network signal.

Abstract: A digital signal processing apparatus having a host processor interfaced to a plurality of signal processing coprocessors through dual port memory elements is disclosed. Coprocessors represent microcoded machines wherein low level instructions directed toward the mechanics of performing a specific signal processing algorithm are contained in microcode. Thus, the host processor programs coprocessors using higher level functional instructions. Each of the coprocessors has a multiply-accumulator, a barrel shifter, an address generator, a hardware loop counter, and a microsequencer.

Abstract: A method of operating a vocoder so that a variable frame rate results while maintaining a constant bit rate is disclosed. A base frame rate remains constant. However, spectral change is measured to determine an appropriate subframe rate within the base frame. Only one of a plurality of separate vector quantization processes is selected in response to spectral change for performance of a vector quantization operation on LPC spectrum coefficients. Each of the plurality of vector quantization operations utilizes its own codebook that contains a different quantity of reference patterns from that contained in the other codebooks. Each vector quantization operation produces a reference pattern descriptor code that contains a different number of bits from that produced by the other vector quantization processes.

Abstract: An apparatus and method is disclosed of providing higher quality speech transmission and reproduction. The present invention consists of a standard 2400 BPS transmitter with the addition of an additional 2400 BPS through a residual signal combined with the standard 2400 BPS signal. The addition of the residual signal gives more information about the speech signal being transmitted and allows more accurate reconstruction of the speech based on the received digital signal. The residual signal is adjusted to phase-align all frequency components to zero, then quantizing only the positive half of the residual signal now symmetric about zero time.

Abstract: A communications system each end of which includes means for analyzing human speech and comparing each word to prestored words for word and speacker recognition, the message then being digitized along with characteristic properties of the speackers voice to form a signal for transmission having a rate of approximately 75 bits per second, transmitting the digitized message to a remote terminal which converts it to a spoken message in the synthesized voice of the original speaker.

Abstract: A multiple rate voice processing system incorporating a complete linear predictive coding algorithm wherein the algorithm is partitioned among a plurality of integrated circuit chips so that all communications between chips occur at low data rates.

Abstract: A linear predictive coding (LPC) voice synthesizer formed as an integrated circuit on a single semiconductor chip, which circuit is programmed to provide the all pole lattice filter method of speech synthesis. The apparatus smoothly interpolates between correlation coefficients during the synthesis operation.

Abstract: In a non-restoring divider circuit each divider step is completed in a single clock pulse by comparing the most significant bits and utilizing a continuous type of comparison to gate data into adding circuits, the summation output of which is introduced into the next most significant gate of the numerator to replace the data previously in the numerator with shifted summation data. Prior to the dividing operation the bits in the three most significant stages of the denominator are compared and the data in the shift registers is shifted by two spaces each clock pulse until the comparison indicates that the data is normalized or until a single clock pulse will complete the normalization of the data.

Abstract: The analyzing apparatus includes a ten stage, all-zero lattice digital filter formed on a single semiconductor chip. A partial correlation coefficient is derived in each stage of the lattice filter in improved coefficient circuitry and the analyzer provides the ten partial correlation coefficients, for a best sample from a plurality of samples, along with the amplitude (R.M.S.), and the residual energy, or the excitation. The correlator uses the products FB, F.sup.2 and B.sup.2, of the residual F and B signals.

Abstract: An absolute magnitude difference function (AMDF) generator for a linear predictive coding (LPC) system including a high speed low pass filter, with the AMDF generator formed on a single semiconductor chip including a data bus, control bus, memory, and a plurality of arithmetic logic units (ALU) for performing a plurality of functions in a reduced number of steps.

Abstract: N (M+1) combining circuits mathematically arranged into M addition rows and a final carry resolution row so as to form N+M-1 columns, each column having an output, an N-bit multiplicand and an M-bit multiplier being connected to the combining circuits to provide digital, repeated addition type multiplication of the numbers represented by the N and M bits. The combining circuits in the final carry resolution row each have a carry bit input connected to the carry bit output of the previous combining circuit and an inverting amplifier is included in the carry propagation line every three or four combining circuits, to regenerate the carry bit. Further the entire multiplying circuit is formed on a single semiconductor chip and includes N inputs pads and N output pads with input latches and output latches for operating on both the N input bits and the M input bits with very little loss in time.

Abstract: A pitch and voiced/unvoiced detector comprising a low pass filter or variable cutoff frequency low pass filter for providing a constant power output, DC shifting and weighting circuits operating on the filtered analog signals, a summing circuit for the filtered and weighted signals, a peak detector with controlled exponential decay time and timing circuits which are used to distinguish pitch and voiced/unvoiced structure in the analog input signal.