Abstract: A process independent digital clock shaping network is described for generating an internal clock signal having preset high state (T.sub.on) and low state (T.sub.off) intervals per cycle from a received clock signal having a substantially constant period but variable T.sub.on and T.sub.off intervals per cycle. The shaping network utilizes a set/reset latch to output the desired clock signal. The set input to the latch receives a set pulse generated at the beginning of each cycle of the received clock signal and the reset input to the latch receives a reset pulse generated by control logic circuitry. The logic circuitry uses the frequency of the received clock signal to generate a reset pulse at the appropriate time for gating of the latch to produce an output clock signal having the desired T.sub.on and T.sub.off intervals per cycle.