Patents by Inventor Bruce A. Loyer

Bruce A. Loyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6957413
    Abstract: A method for including probe locations in an integrated circuit may include specifying probe cells prior to the place and route stage of the design process. The probe cell locations may be specified in a functional description of the integrated circuit, such as an HDL description from which a netlist may be generated. Alternatively, an existing netlist may be edited to include the probe cells on specified nets. The probe locations are included in the physical layout design along with the rest of the integrated circuit components during place and route. The integrated circuit may be fabricated according to the physical layout design so that the fabricated integrated circuit includes the one or more probe locations.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: October 18, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tom McKeone, Bruce A. Loyer
  • Patent number: 6889334
    Abstract: A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: May 3, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Bruce A. Loyer, Pratik M. Mehta
  • Patent number: 6850561
    Abstract: A microcontroller employs an asynchronous serial port for predictably updating a baud divisor during data reception. A write enable to the baud counter ensures that the current value of the baud count in the baud counter is greater than a predetermined number of clocks so that the working baud divisor to be loaded from the working baud divisor register is stabilized. The working baud divisor register is updated during data reception by the serial port by a software write to a visible baud divisor register provided the working baud divisor in the working baud divisor register is not being used to load the baud counter. A working baud divisor register thereby maintains a value guaranteed to be stable by the time a baud counter needs to be reloaded. A visible baud divisor register and the baud counter can be on different, possibly asynchronous clocks.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: February 1, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Melanie D. Typaldos, Bruce A. Loyer, Hock-Koon Lee
  • Patent number: 6642742
    Abstract: A method and apparatus for controlling output impedance of an input/output (I/O) circuit. In one embodiment, an I/O circuit includes a first plurality of resistive elements connected in parallel and a second plurality of resistive elements connected in parallel. Each of the resistive elements includes a control terminal. The control terminal may be used to activate or deactivate the resistive element. The control terminal for each resistive element may be controlled by a control circuit, which may be configured to activate one or more of the resistive elements. Each of the resistive elements of the first plurality may be of substantially different resistances, as may be true with the second plurality of resistive elements. Due to the substantially different resistances of each of the first and second pluralities of resistive elements, the resistive step sizes for the I/O circuit remain substantially equal as additional resistive elements are activated.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: November 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bruce A. Loyer
  • Patent number: 6624681
    Abstract: A circuit and method for stopping a clock tree while maintaining PLL lock. A clock circuit includes a locked loop circuit and a clock tree distribution network. The locked loop circuit receives an input clock signal and generates a PLL output clock depending upon a feedback signal. The clock tree is coupled to the locked loop circuit and conveys the PLL output clock to a plurality of clocked circuit elements. The clock circuit further includes a gating circuit and a feedback delay circuit. The gating circuit is coupled between the locked loop circuit the clock tree distribution network and selectively inhibits the PLL output clock from clocking the clock tree distribution network. The feedback delay circuit provides the feedback signal, which represents a delayed version of the PLL output clock, during operation including when the gating circuit inhibits the PLL output clock from clocking the clock tree.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: September 23, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bruce A. Loyer, Sridhar Subramanian, Michael S. Quimby, Niranjan Venigandla
  • Patent number: 6424186
    Abstract: A circuit for dynamic signal drive strength compensation. A circuit for compensating the drive strength of an output signal includes an output driver stage including a driver circuit and a drive strength control circuit. The driver circuit may be selectively enabled depending upon a drive strength indicator signal. The driver circuit includes a P-channel transistor which has a P input which is controlled by a P-channel control signal. The driver circuit also includes an N-channel transistor which has an N input which is controlled by an N-channel control signal. The drive strength control circuit may generate the respective P-channel and N-channel control signals. The P-channel control signal is prevented from changing while the P-channel transistor is turned on. The N-channel control signal is prevented from changing while the N-channel transistor is turned on.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: July 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael S. Quimby, Bruce A. Loyer
  • Patent number: 6366610
    Abstract: An asynchronous receiver/transmitter provides autobauding with adjustment to a programmable baud rate. A baud divisor is calculated based on a detected size of a start bit. The asynchronous receiver/transmitter provides a plurality of baud divisor replacement registers, each register storing a baud divisor threshold and a baud divisor replacement. The baud divisor is compared to the plurality of programmed baud divisor thresholds. Based on the performed hardware comparison, the baud divisor is automatically replaced by a baud divisor replacement for a particular baud divisor range defined by a baud divisor threshold and including the baud divisor. The baud rate corresponding to this baud divisor replacement represents the appropriate baud rate. Autobauding with adjustment to a programmed baud rate corrects for measurement inaccuracies with respect to the start bit size.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: April 2, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bruce A. Loyer, Melanie D. Typaldos
  • Patent number: 6298396
    Abstract: In a microcontroller employing a buffer descriptor ring direct memory access (DMA) unit, transmission of a packet can be split between multiple buffers. If an error occurs during the transmission of one of the buffers, the buffer descriptor ring DMA unit includes a provision that allows the software to reset the DMA channel to the first buffer containing the failed packet and to restart the transmission of the failed packet, rather than proceeding to the next packet.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: October 2, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bruce A. Loyer, Thai H. Pham, David A. Spilo
  • Patent number: 6266715
    Abstract: A universal serial bus (USB) device or host provides a universal serial bus (USB) controller with a direct memory access (DMA) mode. In a DMA mode, a universal serial bus (USB) transmit endpoint may be programmed for a direct memory access (DMA) transmit channel, or a universal serial bus (USB) receive endpoint may be programmed for a direct memory access (DMA) receive channel. For a USB device, a DMA transmit channel performs data transfer to a universal serial bus (USB) host, and a DMA receive channel handles data transfer from the USB host. For a USB host, a DMA transmit channel performs data transfer to the USB device, and a DMA receive channel handles data transfer from the USB device. A universal serial bus transmit protocol and a universal serial bus receive protocol for the DMA mode of the USB controller permit a maximum packet size of universal serial bus (USB) data to be programmed to a value greater than the physical size of a USB transmit or receive buffer of a USB transmit or receive endpoint.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: July 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bruce A. Loyer, Daniel B. Reents, Allen B. Thor
  • Patent number: 5418786
    Abstract: An asynchronous transfer mode (ATM) layer (10) is coupled to one or more physical layers (PHY layer) (12) via a plurality of conductors (14 and 16). The conductors (14 and 16) allow bi-directional communication of ATM data cells between the layers (10 and 12) using the UTOPIA protocol. In addition, the ATM layer (10) and the PHY layer (12) can communicate one or more status bytes and one or more physical identification (PHY ID) bytes to each other prior to the communication of an ATM data cell. This addition of the communication of one or more status bytes and one or more physical identification (PHY ID) bytes is fully compatible with the currently accepted UTOPIA standard and therefore adds new ATM functionality without compromising the widely-accepted UTOPIA standard for ATM.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: May 23, 1995
    Assignee: Motorola, Inc.
    Inventors: Bruce a. Loyer, Yaron Ben-Arie
  • Patent number: 4700185
    Abstract: A request with response mechanism and method for a local area network controller utilizes an enable bit, a pointer, a counter and an interrupt to create the proper response to a received request with response data frame without the active aid of a host computer.
    Type: Grant
    Filed: December 26, 1984
    Date of Patent: October 13, 1987
    Assignee: Motorola Inc.
    Inventors: Thomas J. Balph, Bruce A. Loyer
  • Patent number: 4652874
    Abstract: A serial communications interface for coupling a physical layer such as a modem to a media access control layer in a token bus network provides data and station management information therebetween on a plurality of bidirectional data lines providing management functions and a unique serial bus for control transfer in addition to communications data.
    Type: Grant
    Filed: December 24, 1984
    Date of Patent: March 24, 1987
    Assignee: Motorola, Inc.
    Inventor: Bruce A. Loyer