Patents by Inventor Bruce A. Newgard

Bruce A. Newgard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIFO in FPGA having logic elements that include cascadable shift registers
    Patent number: 6262597
    Abstract: A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: July 17, 2001
    Assignee: Xilinx, Inc.
    Inventors: Trevor J. Bauer, Bruce A. Newgard, William E. Allaire, Steven P. Young
  • Structure for optionally cascading shift registers
    Patent number: 6118298
    Abstract: A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: September 12, 2000
    Assignee: Xilinx, Inc.
    Inventors: Trevor J. Bauer, Bruce A. Newgard, William E. Allaire, Steven P. Young