Abstract: An RF communications receiver permits greater integration on standard silicon chips and consumes less power than previous receivers. Sub-sampling and discrete-time signal processing techniques are used to frequency down-convert, filter, amplify, and select a desired analog RF channel. A sample-and-hold circuit sub-samples the desired analog RF channel of carrier frequency f.sub.c, thereby down-converting it to a discrete-time image signal of frequency f.sub.i. Successive down-sampling, anti-alias filtering, and amplification of the discrete-time image signal yield a low-frequency discrete-time signal containing a down-converted channel of frequency f.sub.k. The low-frequency discrete-time signal is then digitized, filtered, and demodulated to reveal its baseband information content.

Abstract: An integrated array of pressure transducers capable of producing an analog output voltage representative of the applied pressure is proposed. The individual transducing elements (16) are defined by a three-layer structure including a thin layer of piezoelectric material (10) disposed between a reference potential plate (12) and a plurality of electrodes (15) contained in a silicon substrate (14). A force applied to a localized portion of the reference plate will cause a deflection of the piezoelectric material towards the electrodes on the substrate, inducing a capacitive charge on the electrode in the localized area. This capacitance is stores at a node A associated with the transducing element, and may be interrogated by a sensing circuit (18) located in the silicon substrate. Since the induced charge is directly proportional to the applied force, a measurement of the output voltage from node A will yield a direct indication of the localized force applied to the sensor.

Abstract: A plurality of semiconductor lasers (431-434) and a photodetector (120) are mounted on a silicon substrate (100) having an integrated circuit (101) fabricated therein. The integrated circuit includes a biasing circuit (405) for establishing a threshold current level that is dependent on the output of the photodetector and a modulator circuit (404) for providing a modulation current that is dependent on the digital values in an input signal. A semiconductor switch (406) selects only one of the plurality of semiconductor lasers for activation by the biasing and modulator circuits. The integrated circuit also includes a circuit (408) that operates the semiconductor switch so as to selectively activate a different one of the plurality of semiconductor lasers in response to either a predetermined output from said photodetector or in response to an external supervisory signal.

Abstract: A digital filter includes a pair of serially connected second order sections (200 and 260), each of which includes delay elements arranged to store the number of bits contained in two complete input words. Each filter section also includes simple logic (220, 230, 270 and 280) comprising adder circuits and inverters but no multipliers. The logic combines outputs from the delay element with the filter input to form an intermediate signal which is applied to the input of the delay element. The intermediate signal is also combined with yet other outputs from the delay element to form the filter output. To eliminate clocking complexity within the filter, the logic is not preset or cleared between each input word. Instead, the word length is intentionally increased, and the sign bit of each intermediate word is intentionally repeated as the word is processed in the filter, the extra bits acting as an inter-word buffer and serving to protect against spurious overflow and limit cycle oscillations.

Abstract: An interpolator is arranged to form an increment for each interpolation interval by dividing the difference between the interpolator input and output by a number N indicating the desired number of output samples in the interval. During each interval, the increment is repeatedly added to each output to form the next output.

Abstract: A digital-to-digital converter is arranged to provide "decimated" output samples at rate f.sub.0, each of which represent a group of input samples received at a rate m times greater. Each output is generated using overlapped triangularly weighted accumulation on an interval including 2m preceding input samples. The samples near the beginning and end of each accumulation interval receive the smallest weight, and the samples at the middle of the interval receive the greatest weight. The converter is achievable in integrated circuit form using first and second serially connected accumulators, the first accumulating m input samples without weighting and the second being used to weight the samples so that the first receives m times the weight of the last sample. The output of the first accumulator is increased in scale by the factor "m" and the output of the second accumulator subtracted therefrom. The difference is delayed so that the next m samples may be accumulated.