Abstract: Systems and methods are disclosed for debug path profiling. For example, a processor pipeline may execute instructions. A debug trace circuitry may, responsive to an indication of a non-sequential execution of an instruction by the processor pipeline, generate a record including an address pair and one or more counter values. The address pair may include a first address corresponding to a first instruction before the non-sequential execution and a second address corresponding to a second instruction resulting in the non-sequential execution. The one or more counter values may indicate, for example, a count of instructions executed, a type of instruction executed, cache misses, cycles consumed by cache misses, translation lookaside buffer misses, cycles consumed by translation lookaside buffer misses, and/or processor stalls.

Abstract: A trace circuitry may be configured to receive a selection of one or more types of events possible in a processor core among multiple types of events. The trace circuitry may generate a message including trace information when an event corresponding to the selection occurs in the processor core. The trace information may include an address associated with the event and an indication of the type of event and/or cause for why the event occurred. In some implementations, the trace circuitry may use an event filter to pass events corresponding to the one or more types of events that are selected and block events corresponding to one or more types of events that are not selected. In some implementations, the trace circuitry may generate timestamps based on events to enable measurements between the events.

Abstract: Systems and methods are disclosed for cycle accurate tracing of vector instructions. For example, a system may include a vector unit in communication with a scalar core. The vector unit may include a vector instruction queue that receives vector instructions from the scalar core. The vector unit may also include a vector execution unit that executes vector instructions from the vector instruction queue. The system may also include checkpoints in the vector unit including a first checkpoint including circuitry that sets a first bit for a first clock cycle in which a first vector instruction exits the vector instruction queue, and a second checkpoint including circuitry that sets a second bit for a second clock cycle in which a second vector instruction exits the vector execution unit.

Abstract: Systems and methods are disclosed for processor crash analysis using register sampling. For example, an integrated circuit may include a processor core configured to execute instructions, wherein the processor core includes a program counter register and an exception program counter register (e.g., a machine exception program counter register) that is configured to store a program counter value that was current when an exception occurred; a data store connected to the exception program counter register via an ingress port that is configured to store a copy of an exception program counter value responsive to retirement of an instruction; and an exception program counter capture register, configured to store an exception program counter value from the second data store responsive to a reset signal for the processor core.

Abstract: Systems and methods are disclosed for debug event tracing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core; a data store configured to store a code indicating a cause of an interrupt; a trace buffer configured to store a sequence of debug trace messages; and a debug trace circuitry that is configured to: responsive to a first interrupt to the processor core, generate a first debug trace message including a timestamp and a code from the data store that indicates a cause of the first interrupt; and store the first debug trace message in the trace buffer. In some implementations, the timestamp is generated using a Gray code counter of the integrated circuit.

Abstract: Systems and methods are disclosed for debug path profiling. For example, a processor pipeline may execute instructions. A debug trace circuitry may, responsive to an indication of a non-sequential execution of an instruction by the processor pipeline, generate a record including an address pair and one or more counter values. The address pair may include a first address corresponding to a first instruction before the non-sequential execution and a second address corresponding to a second instruction resulting in the non-sequential execution. The one or more counter values may indicate, for example, a count of instructions executed, a type of instruction executed, cache misses, cycles consumed by cache misses, translation lookaside buffer misses, cycles consumed by translation lookaside buffer misses, and/or processor stalls.

Abstract: A trace circuitry may be configured to receive a selection of one or more types of events possible in a processor core among multiple types of events. The trace circuitry may generate a message including trace information when an event corresponding to the selection occurs in the processor core. The trace information may include an address associated with the event and an indication of the type of event and/or cause for why the event occurred. In some implementations, the trace circuitry may use an event filter to pass events corresponding to the one or more types of events that are selected and block events corresponding to one or more types of events that are not selected. In some implementations, the trace circuitry may generate timestamps based on events to enable measurements between the events.

Abstract: A trace encoder may be connected to a processor core. The trace encoder may be configured to maintain a count of branches that are consecutively taken when executed by the processor core and/or a count of branches that are consecutively not-taken when executed by the processor core. The trace encoder may be configured to send a message including the count.

Abstract: An apparatus for counting occurrences of a plurality of events characterized by unique event numbers includes a random access memory for storing event count numbers at addresses corresponding to the event numbers. The memory is addressed by an event number as the associated event occurs, and the event count number stored at such address is read and latched to an input of an adder. The adder increments the latched event count number and the incremented event count number is then written back into the memory at the current event number address. A buffer is provided to store the current event number whenever the adder overflows as a result of a count. Several such event numbers may be stored in the buffer for subsequent retrieval by an external controller thereby permitting the controller to determine when an event has been counted a fixed number of times and to increment its own internally stored count at a slower rate than the rate at which data is applied to the prescaler.