Abstract: A memory system having a memory cell subject to read and write operations with shadow circuitry including a shadow cell configured to parallel operation of the memory cell. A wordline is connected to the memory cell and bitlines are connected to the memory cell and the shadow cell. Sense circuitry is connected to the bitlines for receiving data from the memory cell. An interlock cell is connected to the sense circuitry and the shadow cell to determine an occurrence of a non-redundant write operation, to provide the non-redundant write operation to the shadow cell, and to have the shadow cell prepare the bitlines for a read operation upon completion of the non-redundant write operation.

Abstract: A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.

Abstract: A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.

Abstract: A logic circuit is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The logic circuit utilizes both SOI field effect transistors (FETs) and SOI diodes to provide for reduced size of the logic circuit and reduced power consumption when the logic circuit is in operation. A method of performing certain logic function is also provided.

Abstract: The present invention provides a sense amplifier that incorporates a logic function. Specifically, that logic function is incorporated into the sense amplifier such that the propagation time of the logic function is avoided and the effective data set-up time of the sense amplifier is reduced. The sense amplifier includes a pair of discharge paths having a true or a complementary version of the logic function associated therewith. When the true or complementary version of the logic function is asserted, one of the discharge paths is turned-on. The output signal that is associated with that discharge path is discharged to a logic low level and the other output signal is pulled to a logic high level. Accordingly, the resulting logic level of the logic function is generated and latched using only the sense amplifier circuit.