Abstract: A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor.

Abstract: A method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models. The method includes collecting power supply noise monitor data from an integrated circuit having one or more power supply noise monitors connected between a power supply and respective scan cells of a scan chain and one or more functional circuits connected to the scan chain by scanning a power supply noise generation pattern into the scan chain and scanning a resultant pattern out of the scan chain; converting the resultant data into actual values of selected power supply parameters; generating simulated values of the selected power supply parameters using a power supply noise simulation model based on design data of the integrated chip; comparing the actual values of the selected power supply parameters to the simulated values of the selected power supply parameters; and modifying the power supply noise simulation model based on the comparing.

Abstract: A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor.

Abstract: A method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models. The method includes collecting power supply noise monitor data from an integrated circuit having one or more power supply noise monitors connected between a power supply and respective scan cells of a scan chain and one or more functional circuits connected to the scan chain by scanning a power supply noise generation pattern into the scan chain and scanning a resultant pattern out of the scan chain; converting the resultant data into actual values of selected power supply parameters; generating simulated values of the selected power supply parameters using a power supply noise simulation model based on design data of the integrated chip; comparing the actual values of the selected power supply parameters to the simulated values of the selected power supply parameters; and modifying the power supply noise simulation model based on the comparing.

Abstract: A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.

Abstract: A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor.

Abstract: An apparatus for directly measuring performance offset of NFET transistors with respect to PFET transistors in CMOS device processing includes a ring oscillator whose frequency is used to measure random across chip variations, as well as correlated across chip variations; a balanced inverter having a input driven by the ring oscillator, wherein the balanced inverter is designed to be formed such that a current drive capability of one or more NFET devices of the inverter is substantially equal to a current drive capability of one or more PFET devices of the inverter at a given operating temperature; and a capacitor coupled to an output of the inverter, with a voltage across the capacitor indicative of whether a skew exists between NFET device performance and PFET device performance.

Abstract: A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.