Patents by Inventor Bruce Barbara
Bruce Barbara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150003182Abstract: A memory device can include a memory array configured to store a first plurality of bits and a second plurality of bits. The memory device may include an address port configured to receive at least a portion of a first address associated with a first command during a first clock cycle, and at least a portion of a second address associated with a second command during the first clock cycle. The memory device may include a plurality of data ports that includes a first data port configured to access the first plurality of bits in response to the receiving of the at least a portion of the first address during the first clock cycle, and a second data port configured to access the second plurality of bits in response to the receiving of the at least a portion of the second address during the first clock cycle.Type: ApplicationFiled: September 15, 2014Publication date: January 1, 2015Inventors: Dinesh Maheshwari, Bruce Barbara, John Marino
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Publication number: 20140293717Abstract: A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.Type: ApplicationFiled: January 14, 2014Publication date: October 2, 2014Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Dinesh Maheshwari, Bruce Barbara, John Marino
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Patent number: 8630111Abstract: A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.Type: GrantFiled: April 9, 2013Date of Patent: January 14, 2014Assignee: Cypress Semiconductor CorporationInventors: Dinesh Maheshwari, Bruce Barbara, John Marino
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Publication number: 20130223165Abstract: A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.Type: ApplicationFiled: April 9, 2013Publication date: August 29, 2013Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Dinesh Maheshwari, Bruce Barbara, John Marino
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Patent number: 8472276Abstract: A system and method is provided for hot de-latch of a parasitic device in an integrated circuit (IC) that restores the IC to normal operation without de-powering the IC or resulting in a loss of data. In one embodiment the method, includes reducing a voltage supplied to at least a portion of the IC from a normal operation voltage to a de-latch voltage for a time to de-latch the parasitic device without de-powering the IC. Other embodiments are also disclosed.Type: GrantFiled: February 28, 2011Date of Patent: June 25, 2013Assignee: Cypress Semiconductor CorporationInventors: Bruce Barbara, Morgan Whately
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Patent number: 8095747Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.Type: GrantFiled: September 26, 2008Date of Patent: January 10, 2012Assignee: Cypress Semiconductor CorporationInventors: Bruce Barbara, Gabriel Li, Thinh Tran, Joseph Tzou
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Publication number: 20100082861Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.Type: ApplicationFiled: September 26, 2008Publication date: April 1, 2010Applicant: Cypress Semiconductor CorporationInventors: Bruce Barbara, Gabriel Li, Thinh Tran, Joseph Tzou
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Publication number: 20060217906Abstract: A fault detection and protection circuit can include a comparing circuit (e.g., a comparator or a detector) that can be connected to a power line supplying power to an electronic device being tested. The comparing circuit can be configured to detect a fault in which the power line is shorted to ground. For example, the electronic device being tested may have a fault in which its power terminals are shorted to ground. Upon detection of such a fault, the comparing circuit activates one or more switches that shunt capacitors or other energy storage devices on the power line to ground. The comparing circuit may alternatively or in addition activate one or more switches that disconnect the power supply supplying power to the electronic device under test from probes contacting the electronic device.Type: ApplicationFiled: December 19, 2005Publication date: September 28, 2006Inventors: Bruce Barbara, Charles Miller
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Publication number: 20060076690Abstract: Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.Type: ApplicationFiled: June 24, 2005Publication date: April 13, 2006Applicant: FormFactor, Inc.Inventors: Igor Khandros, Charles Miller, Bruce Barbara, Barbara Vasquez
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Publication number: 20060040417Abstract: Resilient spring contacts for use in wafer test probing are provided that can be manufactured with a very fine pitch spacing and precisely located on a support substrate. The resilient contact structures are adapted for wire bonding to an electrical circuit on a space transformer substrate. The support substrates with attached spring contacts can be manufactured together in large numbers and diced up and tested before attachment to a space transformer substrate to improve yield. The resilient spring contacts are manufactured using photolithographic techniques to form the contacts on a release layer, before the spring contacts are epoxied to the support substrate and the release layer removed. The support substrate can be transparent to allow alignment of the contacts and testing of optical components beneath. The support substrate can include a ground plane provided beneath the spring contacts for improved impedance matching.Type: ApplicationFiled: August 19, 2004Publication date: February 23, 2006Applicant: FormFactor, Inc.Inventors: Benjamin Eldridge, Bruce Barbara
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Patent number: 4928266Abstract: A static memory device is disclosed having an array of static memory cells, each memory cell having first and second cross-coupled inverters. All of the memory cells have distinct power voltage connections to the first and second inverters of each memory cell. When a reset signal occurs, the device's reset apparatus generates a voltage imbalance on the power voltage connections so that distinct voltage levels are applied to the first and second cross-coupled inverters of each memory cell. The voltage imbalance causes all of the memory cells in the array to be set into a predetermined state. In a preferred embodiment, the power voltage connections include a common high voltage power connection to all of the memory cells and distinct low voltage power connections to the first and second inverters of each memory cell.Type: GrantFiled: May 26, 1988Date of Patent: May 22, 1990Assignee: Visic, Inc.Inventors: Robert A. Abbott, Bruce Barbara, Richard S. Roy