Patents by Inventor Bruce Bennett Doris
Bruce Bennett Doris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8018005Abstract: A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.Type: GrantFiled: June 25, 2010Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Bruce Bennett Doris, William K. Henson, Richard Stephen Wise, Hongwen Yan
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Publication number: 20100258875Abstract: A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.Type: ApplicationFiled: June 25, 2010Publication date: October 14, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Bennett Doris, William K. Henson, Richard Stephen Wise, Hongwen Yan
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Patent number: 7749830Abstract: A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient.Type: GrantFiled: February 6, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Bruce Bennett Doris, William K. Henson, Richard Stephen Wise, Hongwen Yan
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Patent number: 7602021Abstract: A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.Type: GrantFiled: February 2, 2007Date of Patent: October 13, 2009Assignee: International Business Machines CorporationInventors: Bruce Bennett Doris, Diane C. Boyd, Huilong Zhu
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Publication number: 20090194820Abstract: A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient.Type: ApplicationFiled: February 6, 2008Publication date: August 6, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Bennett Doris, William K. Henson, Richard Stephen Wise, Hongwen Yan
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Patent number: 6873010Abstract: An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.Type: GrantFiled: October 10, 2003Date of Patent: March 29, 2005Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Omer H. Dokumaci, Bruce Bennett Doris, Oleg Gluschenkov, Rajarao Jammy, Jack Allen Mandelman
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Publication number: 20040075111Abstract: An integrated circuit such as a memory chip with embedded logic or a logic array or processor with imbedded large cache memory in which all significant sources of incompatibility between array transistors and high performance logic transistors are resolved. The integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, F, and memory cell areas or 8-12 F2 and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel length of 0.7 F or less, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness.Type: ApplicationFiled: October 10, 2003Publication date: April 22, 2004Inventors: Dureseti Chidambarrao, Omer H. Dokumaci, Bruce Bennett Doris, Oleg Gluschenkov, Rajarao Jammy, Jack Allan Mandelman
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Patent number: 6709926Abstract: An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.Type: GrantFiled: May 31, 2002Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Omer H. Dokumaci, Bruce Bennett Doris, Oleg Gluschenkov, Rajarao Jammy, Jack Allan Mandelman
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Publication number: 20030224573Abstract: An integrated circuit such as a memory chip with embedded logic or a logic array or processor with imbedded large cache memory in which all significant sources of incompatibility between array transistors and high performance logic transistors are resolved. The integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, F, and memory cell areas or 8-12 F2 and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel length of 0.7F or less, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness.Type: ApplicationFiled: May 31, 2002Publication date: December 4, 2003Applicant: International Business Machines CorporationInventors: Dureseti Chidambarrao, Omer H. Dokumaci, Bruce Bennett Doris, Oleg Gluschenkov, Rajarao Jammy, Jack Allan Mandelman
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Patent number: 6613602Abstract: A method and system for forming a thermoelement for a thermoelectric cooler is provided. In one embodiment a substrate having a plurality of pointed tips covered by a metallic layer is formed. Portions of the metallic layer are covered by an insulator and other portions of the metallic layer are exposed. Next, a patterned layer of thermoelectric material is formed by depositions extending from the exposed portions of the metallic layer in the presence of a deposition mask. Finally, a metallic layer is formed to selectively contact the patterned layer of thermoelectric material.Type: GrantFiled: December 13, 2001Date of Patent: September 2, 2003Assignee: International Business Machines CorporationInventors: Emanuel Israel Cooper, Steven Alan Cordes, David R. DiMilia, Bruce Bennett Doris, James Patrick Doyle, Uttam Shyamalindu Ghoshal, Robin Altman Wanner
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Publication number: 20030113950Abstract: A method and system for forming a thermoelement for a thermoelectric cooler is provided. In one embodiment a substrate having a plurality of pointed tips covered by a metallic layer is formed. Portions of the metallic layer are covered by an insulator and other portions of the metallic layer are exposed. Next, a patterned layer of thermoelectric material is formed by depositions extending from the exposed portions of the metallic layer in the presence of a deposition mask. Finally, a metallic layer is formed to selectively contact the patterned layer of thermoelectric material.Type: ApplicationFiled: December 13, 2001Publication date: June 19, 2003Applicant: International Business Machines Corp.Inventors: Emanuel Israel Cooper, Steven Alan Cordes, David R. Dimilia, Bruce Bennett Doris, James Patrick Doyle, Uttam Shyamalindu Ghoshal, Robin Altman Wanner