Patents by Inventor Bruce Block

Bruce Block has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194533
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 13, 2024
    Applicant: Intel Corporation
    Inventors: Valluri R. RAO, Patrick MORROW, Rishabh MEHANDRU, Doug INGERLY, Kimin JUN, Kevin O'BRIEN, Paul FISCHER, Szuya S. LIAO, Bruce BLOCK
  • Patent number: 11854894
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Valluri R. Rao, Patrick Morrow, Rishabh Mehandru, Doug Ingerly, Kimin Jun, Kevin O'Brien, Paul Fischer, Szuya S. Liao, Bruce Block
  • Publication number: 20210175124
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Applicant: Intel Corporation
    Inventors: Valluri R. RAO, Patrick MORROW, Rishabh MEHANDRU, Doug INGERLY, Kimin JUN, Kevin O'BRIEN, Paul FISCHER, Szuya S. LIAO, Bruce BLOCK
  • Patent number: 10872820
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Bruce Block, Valluri R. Rao, Patrick Morrow, Rishabh Mehandru, Doug Ingerly, Kimin Jun, Kevin O'Brien, Paul Fischer, Szyua S. Liao
  • Publication number: 20200035560
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Application
    Filed: August 25, 2017
    Publication date: January 30, 2020
    Applicant: Intel Corporation
    Inventors: Bruce BLOCK, Valluri R. RAO, Patrick MORROW, Rishabh MEHANDRU, Doug INGERLY, Kimin JUN, Kevin O'BRIEN, Patrick MORROW, Szyua S. LIAO
  • Patent number: 8487249
    Abstract: The apparatus introduces a second adjustable resonant point in a QMS at a frequency that is close to a multiple of the fundamental frequency by adjusting driving point impedance characteristics of the QMS. The apparatus measures the first and second resonant point of the QMS to account for changes in the operational characteristics of the QMS.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 16, 2013
    Assignee: The Regents of the University of Michigan Office of Technology Transfer
    Inventors: Daniel Gershman, Bruce Block, Martin Rubin, Thomas Zurbuchen
  • Publication number: 20120145892
    Abstract: The apparatus introduces a second adjustable resonant point in a QMS at a frequency that is close to a multiple of the fundamental frequency by adjusting driving point impedance characteristics of the QMS. The apparatus measures the first and second resonant point of the QMS to account for changes in the operational characteristics of the QMS.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 14, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Daniel Gershman, Bruce Block, Martin Rubin, Thomas Zurbuchen
  • Publication number: 20070252187
    Abstract: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.
    Type: Application
    Filed: June 26, 2007
    Publication date: November 1, 2007
    Inventors: Richard List, Bruce Block, Ruitao Zhang
  • Publication number: 20070235877
    Abstract: A semiconductor device is described with a photodetector embedded within and a method of manufacturing the same. The photodetector may be formed above the conductive layers within the device and may detect transmitted light from the top side of the device. The process of manufacturing the device may include a damascene or a subtractive etch process.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 11, 2007
    Inventors: Miriam Reshotko, Bruce Block, David Kencke
  • Publication number: 20070081760
    Abstract: An apparatus and method for embedding a laser source on a semiconductor substrate and an optical interconnect to couple the laser source to internal components of the semiconductor substrate. An on-die waveguide is integrated on the semiconductor substrate. A package waveguide is disposed on the semiconductor substrate and evanescently coupled to the on-die waveguide. The laser source is embedded within the packaged waveguide to provide an optical signal to the on-die waveguide via the package waveguide.
    Type: Application
    Filed: September 26, 2005
    Publication date: April 12, 2007
    Inventors: Daoqiang Lu, Bruce Block, Dongming He
  • Publication number: 20060263924
    Abstract: A photosensitive device for enabling high speed detection of electromagnetic radiation. The device includes recessed electrodes for providing a generally homogeneous electric field in an active region. Carriers generated in the active region are detected using the recessed electrodes.
    Type: Application
    Filed: July 31, 2006
    Publication date: November 23, 2006
    Inventors: Miriam Reshotko, Shaofeng Yu, Bruce Block
  • Publication number: 20060188827
    Abstract: A method of protecting a sensitive layer from harsh chemistries. The method includes forming a first sensitive layer, forming a second layer upon the first layer, then forming a third layer over the second layer. The third layer is utilized as a mask during patterning of the second layer. During patterning, however, the second layer is only partially etched, thus leaving a buffer layer overlying the first layer. The third layer is completely removed while the buffer layer protects the first layer from the harsh chemicals that are utilized to remove the third layer. Then, the buffer layer is carefully removed down to the surface of the first layer.
    Type: Application
    Filed: March 6, 2006
    Publication date: August 24, 2006
    Inventors: Justin Brask, Bruce Block, Uday Shah
  • Publication number: 20060138592
    Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.
    Type: Application
    Filed: December 23, 2005
    Publication date: June 29, 2006
    Inventors: Bruce Block, Richard List, Ruitao Zhang
  • Publication number: 20060093967
    Abstract: An integrated waveguide and photodetector which are evanescently coupled, and methods of making such integrated waveguide and photodetector.
    Type: Application
    Filed: December 15, 2005
    Publication date: May 4, 2006
    Inventor: Bruce Block
  • Publication number: 20060007969
    Abstract: A pulse laser generates a pulse train. A modulator receives the pulse train and a data signal. The modulator encodes the data signal onto the pulse train by selectively passing pulses.
    Type: Application
    Filed: March 31, 2004
    Publication date: January 12, 2006
    Inventors: Brandon Barnett, Bruce Block
  • Publication number: 20050259380
    Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.
    Type: Application
    Filed: January 27, 2004
    Publication date: November 24, 2005
    Inventors: Bruce Block, Richard List
  • Publication number: 20050202312
    Abstract: A photosensitive device for enabling high speed detection of electromagnetic radiation. The device includes recessed electrodes for providing a generally homogeneous electric field in an active region. Carriers generated in the active region are detected using the recessed electrodes.
    Type: Application
    Filed: May 4, 2005
    Publication date: September 15, 2005
    Inventors: Miriam Reshotko, Shaofeng Yu, Bruce Block
  • Publication number: 20050123244
    Abstract: Waveguide couplers to efficiently couple light from one waveguide to another with different cross sections, including but not limited to waveguides in compact integrated packages fabricated on substrates.
    Type: Application
    Filed: December 3, 2003
    Publication date: June 9, 2005
    Inventors: Bruce Block, Brandon Barnett, Paul Davids
  • Publication number: 20050111806
    Abstract: A semiconductor based structure containing substantially smoothed waveguides having a rounded surface is disclosed, as well as methods of fabricating such a structure. The substantially smoothed waveguides may be formed of waveguide materials such as amorphous silicon or stoichiometric silicon nitride. The substantially smoothed waveguides are formed with an isotropic wet etch combined with sonic energy.
    Type: Application
    Filed: November 24, 2003
    Publication date: May 26, 2005
    Inventors: Justin Brask, Bruce Block
  • Publication number: 20050054199
    Abstract: Optical waveguide devices having adjustable waveguide cladding wherein the waveguide cladding is adjustable by using an external control or stimulus to change an optical characteristic of the waveguide cladding, e.g., the refractive index of the cladding. Such waveguide devices may be designed to have certain features that are suitable for monolithically integrated opto-electronic devices and systems.
    Type: Application
    Filed: September 8, 2003
    Publication date: March 10, 2005
    Inventors: Bruce Block, Brandon Barnett, Paul Davids