Abstract: A First-In-First-Out (FIFO) memory device includes a FIFO memory block, a data input interface that writes data into the FIFO memory block in synchronization with a first clock, and a data output interface that reads the data from the FIFO memory block in synchronization with a second clock. The data input interface provides a first indication to the data output interface that the received data has been written into the FIFO memory block. The first indication persists until reset by the data output interface. The data output interface provides a second indication to the data input interface that the received data has been read from the FIFO memory block. The second indication persists until reset by the data input interface.

Abstract: A field effect transistor (FET) includes a first source/drain terminal, a body terminal, and a second source/drain terminal. A bi-directional N-channel FET circuit includes a biasing circuit which couples the body terminal of the bi-directional FET to one of its first and second source/drain terminals having a lesser voltage when the first and second source/drain voltages differ by more than a threshold voltage. When the voltages differ by a threshold voltage or less, the body terminal floats at a voltage no higher than a diode drop above the lesser of the two source/drain voltages, and at a voltage no lower than a threshold voltage below the higher of the two source/drain voltages. An analogous bi-directional P-channel FET circuit is also described. Body effect is reduced because the body terminal of the FET is maintained at a voltage at or near the voltage of the effective source terminal at all times, irrespective of which of the two source/drain terminals is the effective source terminal.

Abstract: A retriggerable edge detector is provided having a means for receiving digital input signals, at least two signal transmitting paths connected to that signal receiving means, one of which paths transmits the input signal with predetermined delay, output gating means for producing an output signal as a function of the signals transmitted by the signal paths, and wherein logic means are provided in the delay signal path so as to cause the output gating means to produce a signal output pulse of predetermined, constant width in response to the last of one or more input signals, irrespective of the time between inputting of these input signals. The logic means provides for a portion of the delay signal path to be reset to its input state in a shorter time than the total delay line propagation time.