Abstract: A method and circuit for synchronizing input data with a sample clock in which, for each sample clock cycle, the position of input data transitions relative to an acceptable neutral zone is detected. The neutral zone is of predetermined time duration and is positioned in a predetermined location relative to the active edge of the clock signal. If the transition occurs during the neutral zone no corrective action is warranted. If the data transitions move beyond the neutral zone, into a predetermined time interval on either side of the active edge, this event is captured and used by control logic to effect a return of the data transitions to a location within the neutral zone.

Abstract: An improved sequence generator. The inventive generator (10) is adapted for use with a source (12) for providing successive bits of random data. The invention (10) includes a shift register (18) with a feedback loop. The shift register (18) stores bits of random data. Input to the shift register (18) is determined by a switch (16) which selects between the random data source (12), in a first mode of operation, and the feedback loop, in a second mode of operation. A control logic circuit (20) triggers the switch from the second mode to the first mode, for one clock cycle, as the random data source (12) provides a each successive bit of random data. Thus, optimum performance is obtained without the need to gate clock signals or to control the operation of the shift register.