Abstract: Actuation mechanisms driven by rotary motors are described whereby linear movement of a mechanical component, typically a lens barrel, is effected without rotating the linear moving component. For mechanisms driven by miniature piezoelectric motors, this is accomplished by driving a rotor which in turn causes linear, and only linear, movement of a lens barrel according to structures described in different embodiments. A preferred embodiment includes a threaded rotor moving both rotationally and axially that drives a two-piece lens barrel assembly. Another embodiment includes a rotor having a grooved split ring on its outer surface that does not move axially and drives a lens barrel through a threaded interface. Another embodiment includes a two-piece rotor that does not move axially and drives a lens barrel through a threaded interface. Typically, anti-rotation pins and corresponding grooves in a fixed structure are used to prevent the lens barrel from rotating.

Abstract: A miniature piezoelectric motor is described whereby in one embodiment teethed protrusions emanating inward from an annular-shaped stator engage with a rotor as the stator deforms in response to stresses applied to the stator by PZT pads attached thereto. The PZT pads are driven by voltage waveforms according to either a standing or traveling wave method and each deformation of the stator applies a tangential force to the rotor via a plurality of teethed protrusions, thereby moving the rotor a small amount. Flat PZT pads attached to flat facets on conductive surfaces of the stator are utilized in order to increase manufacturability and reduce cost. Configuration of the facets tunes the resonant frequency of the stator ensuring that the motor operates in the ultrasonic range, and also tunes the voltage level of drive signal required. Placement of PZT elements on the inner circumferential surface further optimizes overall motor size.

Abstract: A RAM module that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the RAM module to perform its access and pre-charge during the dips and posts of the optimized clock signal, the RAM module can perform multiple accesses and pre-charges during one clock cycle. The RAM module can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.

Abstract: A synchronous SRAM chip that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the synchronous SRAM chip to perform its access and pre-charge during the dips and posts of the optimized clock signal, the synchronous SRAM chip can perform multiple accesses and pre-charges during one clock cycle. The SRAM chip can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.