Patents by Inventor Bruce Cockburn

Bruce Cockburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Decoder for low-density parity-check convolutional codes
    Patent number: 8078933
    Abstract: Decoder for low-density parity check convolutional codes. In at least some embodiments, a decoder (200) for arbitrary length blocks of low-density, parity-check codes includes a plurality of interconnected processors (202), which further include a plurality of interconnected nodes. A memory can be interconnected with the nodes to store intermediate log likelihood ratio (LLR) values based on channel LLR values. Thus, LLR values having successively improved accuracy relative to the channel LLR values can be output from each processor, and eventually used to decision information bits. In some embodiments, the memory is a random access memory (RAM) device that is adapted to store the intermediate LLR values in a circular buffer. Additionally, a storage device such as a read-only memory (ROM) device can be used to generate a predetermined plurality of addresses for reading and writing LLR values.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: December 13, 2011
    Assignee: The Governors of the University of Alberta
    Inventors: Stephen Bates, Christian Schlagel, Bruce Cockburn, Vincent Gaudet
  • Decoder for Low-Density Parity-Check Convolutional Codes
    Publication number: 20080195913
    Abstract: Decoder for low-density parity check convolutional codes. In at least some embodiments, a decoder (200) for arbitrary length blocks of low-density, parity-check codes includes a plurality of interconnected processors (202), which further include a plurality of interconnected nodes. A memory can be interconnected with the nodes to store intermediate log likelihood ratio (LLR) values based on channel LLR values. Thus, LLR values having successively improved accuracy relative to the channel LLR values can be output from each processor, and eventually used to decision information bits. In some embodiments, the memory is a random access memory (RAM) device that is adapted to store the intermediate LLR values in a circular buffer. Additionally, a storage device such as a read-only memory (ROM) device can be used to generate a predetermined plurality of addresses for reading and writing LLR values.
    Type: Application
    Filed: December 14, 2005
    Publication date: August 14, 2008
    Applicant: THE GOVERNORS OF THE UNIVERSITY OF ALBERTA
    Inventors: Stephen Bates, Christian Schlagel, Bruce Cockburn, Vincent Gaudet