Patents by Inventor Bruce D. Gittleman

Bruce D. Gittleman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170073805
    Abstract: A method of making multilayer thin film Li-ion devices that can involve direct current (DC) sputtering of a metal current collector film or pulsed DC sputtering (PDC) of a transparent conducting oxide (TCO) onto a substrate, depositing a very thin metal diffusion barrier using high power impulse magnetron sputtering (HPIMS), depositing one or more ion storage layers or a cathode layer and an electrolyte layer by PDC sputtering or reactive PDC sputtering of a non-insulating target, and depositing a TCO via PDC sputtering or depositing an anode layer by PDC sputtering and a metal current collector by DC sputtering, the combination of these layers depending on the particular device being fabricated.
    Type: Application
    Filed: April 29, 2016
    Publication date: March 16, 2017
    Inventors: Bruce D. Gittleman, David Alie
  • Patent number: 7901545
    Abstract: An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a process which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang within a vacuum chamber. The iPVD system is operated at low target power and high pressure >50 mT to sputter material from the target. RF energy is coupled into the chamber to form a high density plasma. A small RF bias (less than a few volts) can be applied to aid in enhancing the coverage, especially at the bottom.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: March 8, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Frank M. Cerio, Jr., Jacques Faguet, Bruce D. Gittleman, Rodney L. Robison
  • Publication number: 20090321247
    Abstract: A method is provided of operating a deposition system to deposit coating material into high aspect ratio nano-sized features on a patterned substrate that enhances sidewall coverage compared to field area and bottom surface coverage while minimizing or eliminating overhang. The method includes performing a process step with a gross field area deposition rate of about 25 to 70 nm/min and simultaneously etching the barrier layer to establish a net field area deposition rate of about 5 to 40 nm/min. The method may also include first performing a protective layer deposition step with a field area deposition rate of about 5 to 20 nm/min without etching the underlying surface then performing a surface modification step with gross deposition and simultaneous etching at a field modification net deposition rate of about ?10 to +40 nm/min.
    Type: Application
    Filed: September 8, 2009
    Publication date: December 31, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Frank M. Cerio, JR., Jacques Faguet, Bruce D. Gittleman, Rodney L. Robison