Abstract: Method and apparatus for converting multibit pixel data to a lesser number of bit pixel data and re-expanding the compressed data. Luminance data for each pixel is established as the 5 most significant bits of the original luminance signal. The chrominance information for groups of pixels is subsampled, and a common chrominance value assigned to each of the pixels in a group. The resulting compressed pixels may be 8 bits wide providing economical possibilities to store the 8 bit wide data. The data is expanded for display by adding lower order data bits to the compressed luminance signal data bits. A subsampled chrominance data signal is appended to the expanded luminance data for display.

Abstract: A color display device which includes dither apparatus for each primary color to be displayed. A dither matrix provides a dither signal output as a function of the position of a pixel on the color display device. An input primary color signal includes an integer signal and a fraction signal. The integer signal is incremented by an incrementer. There is means for providing an output primary color signal which is the incremented signal whenever a predetermined relationship exists between the dither signal and the fraction signal, and which is the integer signal whenever the predetermined relationship does not exist.

Abstract: A method for improving the viewing quality of a CRT display image without increasing resolution of the display. With the invention disclosed herein, characters are apparently positioned at sub-pixel locations to improve the viewing quality of a CRT display image. This apparent positioning is accomplished by changing intensity values assigned to pixels on a CRT display. In the preferred embodiment, the change in intensity values is effected by linear interpolation with intensity values of neighboring pixels to yield second intensity values. These second intensity values, then, improve the viewing quality of the CRT display image.

Abstract: The system includes a plurality of memory units each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete section of a larger array. The units are interconnected through common interconnection buses and selectively actuable input and output gate connections to those buses to provide for selective shifting of bits between units to change the bit array.