Abstract: A method and system is provided for detecting and correcting non-deterministic data that provides substantially real-time validation results and maximizes flexibility for the device manufacturer while reducing test costs. The automatic test apparatus and method can correct non-determinism caused by cycle slipping at the beginning of data transmission, between packets of data being transmitted and out-of-order data types of non-determinism. A data validation circuit is coupled to the receiver for validating the packet data based on expected packet data stored in a vector memory.

Abstract: An integrated circuit test apparatus according to an exemplary embodiment includes a first memory section configured to store processor procedures and a second memory section configured to simultaneously store parallel integrated circuit test vectors and serial integrated circuit test vectors. A processor is coupled to the first memory section and to the second memory section. The processor is configured to execute the processor procedures to simultaneously manipulate the parallel integrated circuit test vectors and the serial integrated circuit test vectors located in the second memory to test an integrated circuit. Advantages of the invention include the ability to simultaneously store serial and parallel test vectors and to test a device under test (DUT) with simultaneous serial and parallel test vectors. The combination of serial and parallel test vectors increases performance and efficiency of the test apparatus.