Abstract: A method of fabricating silicon nanostructures includes preparing a silicon wafer as a substrate; forming an oxide layer hardmask directly on the silicon substrate; patterning and etching the oxide hardmask; wet etching the silicon wafer to remove oxide to reduce the size of the oxide hardmask and to form nanostructure elements; and dry etching, in one or more steps, the silicon wafer using the oxide hardmask to form a desired nanostructure having substantially parallel vertical sidewalls thereon.

Abstract: A method of fabricating a grayscale reticle includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer with a pattern for the silicon nitride layer; removing the photoresist; cleaning the quartz substrate and the remaining layers; oxidizing the quartz substrate and the layers thereon, thereby converting the silicon-rich oxide layer to a transparent silicon dioxide layer; removing the remaining silicon nitride layer; forming the quartz substrate and the silicon dioxide thereon into a reticle; and using the reticle to pattern a microlens array.

Abstract: A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.

Abstract: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.

Abstract: A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

Abstract: A method of forming a microlens array includes preparing a substrate; fabricating a photosensitive array on the substrate; depositing a layer of lens material on the photosensitive array; depositing and patterning photoresist on the lens material, wherein patterning includes forming a photoresist region having a solid curved upper surface and a substantially rectangular base on the lens material layer; developing the photoresist; reflowing the photoresist; and processing the lens material for form a microlens array.

Abstract: An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region; forming a high-k dielectric overlying the surface channel; and, forming a gate electrode overlying the high-k dielectric. Typically, the surface channel is a metal oxide, and may be one of the following materials: indium oxide (In2O3), ZnO, RuO, ITO, or LaX-1SrXCoO3. In some aspects, the method further comprises: depositing a placeholder material overlying the surface channel; and, etching the placeholder material to form a gate region overlying the surface channel. In one aspect, the high-k dielectric is deposited prior to the deposition of the placeholder material. Alternately, the high-k dielectric is deposited following the etching of the placeholder material.

Abstract: A method of microlens fabrication for use in a photosensor includes preparing a photodetector element array which is sensitive to light in a specific color domain and depositing microlens material on the photodetector element array. The structure is coated with photoresist, and the photoresist is masked and exposed in a separate exposure for each color in the color domain. The photoresist is developed and the microlens material etched to form a microlens array.

Abstract: A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

Abstract: A two dimensional vernier is provided along with a method of fabrication. The two dimensional vernier has a reference array patterned into a substrate, or a material overlying the substrate. An active array is patterned into photoresist overlying the substrate or the material. Both the reference array and the active array each comprise a two dimensional array of shapes. A difference between a combination of size or spacing of the shapes in each array determines vernier resolution. Vernier range is determined by a combination of vernier resolution and an integer related to a total number of shapes along a given axis. The two dimensional vernier allows an operator to readily measure the misalignment of a pattern to be processed relative to a previous pattern in two dimensions using a microscope. The two dimensional vernier reduces, or eliminates, repositioning of the microscope to determine both x-axis misalignment and y-axis misalignment.

Abstract: A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer on the bottom electrode layer; depositing a noble metal top electrode layer on the ferroelectric layer; depositing an adhesion layer on the top electrode layer; depositing a hard mask layer on the adhesion layer; patterning the hard mask; etching the noble metal top electrode layer in an initial etching step at a predetermined RF bias power, which produces etching residue; and over etching the noble metal top electrode layer and ferroelectric layer at an RF bias power lower than that of the predetermined RF bias power to remove etching residue from the initial etching step.

Abstract: A two dimensional vernier is provided along with a method of fabrication. The two dimensional vernier has a reference array patterned into a substrate, or a material overlying the substrate. An active array is patterned into photoresist overlying the substrate or the material. Both the reference array and the active array each comprise a two dimensional array of shapes. A difference between a combination of size or spacing of the shapes in each array determines vernier resolution. Vernier range is determined by a combination of vernier resolution and an integer related to a total number of shapes along a given axis. The two dimensional vernier allows an operator to readily measure the misalignment of a pattern to be processed relative to a previous pattern in two dimensions using a microscope. The two dimensional vernier reduces, or eliminates, repositioning of the microscope to determine both x-axis misalignment and y-axis misalignment.

Abstract: A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.

Abstract: A two dimensional vernier is provided along with a method of fabrication. The two dimensional vernier has a reference array patterned into a substrate, or a material overlying the substrate. An active array is patterned into photoresist overlying the substrate or the material. Both the reference array and the active array each comprise a two dimensional array of shapes. A difference between a combination of size or spacing of the shapes in each array determines vernier resolution. Vernier range is determined by a combination of vernier resolution and an integer related to a total number of shapes along a given axis. The two dimensional vernier allows an operator to readily measure the misalignment of a pattern to be processed relative to a previous pattern in two dimensions using a microscope. The two dimensional vernier reduces, or eliminates, repositioning of the microscope to determine both x-axis misalignment and y-axis misalignment.

Abstract: A memory device formed from selectively deposited PGO and a method for selectively forming a Pb5Ge3O11 (PGO) thin film memory device are provided. The method comprises: forming a silicon (Si) substrate; forming a silicon oxide film overlying the substrate; forming a patterned bottom electrode overlying the silicon oxide film; selectively depositing a PGO film overlying the bottom electrode; annealing; and, forming a top electrode overlying the PGO film. Selectively depositing a PGO film overlying the bottom electrodes includes: depositing a seed layer of PGO; and, forming a c-axis oriented PGO layer overlying the seed layer.

Abstract: A memory device formed from selectively deposited PGO and a method for selectively forming a Pb5Ge3O11 (PGO) thin film memory device are provided. The method comprises: forming a silicon (Si) substrate; forming a silicon oxide film overlying the substrate; forming a patterned bottom electrode overlying the silicon oxide film; selectively depositing a PGO film overlying the bottom electrode; annealing; and, forming a top electrode overlying the PGO film. Selectively depositing a PGO film overlying the bottom electrode includes: depositing a seed layer of PGO; and, forming a c-axis oriented PGO layer overlying the seed layer.

Abstract: A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.

Abstract: A method of forming a PGO thin film on a high-k dielectric includes preparing a silicon substrate, including forming a high-k gate oxide layer thereon; patterning the high-k gate oxide; annealing the substrate in a first annealing step; placing the substrate in a MOCVD chamber; depositing a PGO thin film by injecting a PGO precursor into the MOCVD chamber; and annealing the structure having a PGO thin film on a high-k gate oxide in a second annealing step.

Abstract: A method of fabricating a CMOS have self-aligned shallow trench isolation, includes preparing a silicon substrate; forming a gate stack; depositing a layer of first polysilicon; trenching the substrate by shallow trench isolation to form a trench; filling the trench with oxide; depositing a second layer of polysilicon wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer; depositing a sacrificial oxide layer having a thickness of at least 1.5× that of the first polysilicon layer; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.

Abstract: A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.