Patents by Inventor Bruce Duewer
Bruce Duewer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10509624Abstract: Audio content in a single-bit audio stream can be reproduced at a transducer by mapping the single-bit audio stream to symbols in a multi-bit audio stream. Volume control may be implemented, in part, in the digital domain and, in part, in the analog domain. In the digital domain, when converting the single-bit audio stream to a plurality of symbols, the plurality of symbols is selected based, at least in part, on audio content of the single-bit audio stream and a desired volume level. In the analog domain, when converting an analog current signal output from a current-steering DAC processing the plurality of symbols to an analog voltage signal, an analog gain value may be selected based, at least in part, on the desired volume level.Type: GrantFiled: September 15, 2017Date of Patent: December 17, 2019Assignee: Cirrus Logic, Inc.Inventors: Bruce Duewer, Dylan Hester, Shafagh Kamkar
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Patent number: 10424311Abstract: An audio processing circuit may have a first path for processing multi-bit audio signals in parallel with a second path for processing single-bit audio signals. The parallel paths may share a common input node for receiving audio data and a common output node for reproducing audio at a transducer. Each path may have a volume control for adjusting an output of the path. The audio processing circuit may determine a type of an audio signal received at the input. The path not corresponding to the detected type of the audio signal is muted, and the path corresponding to the detected type of audio signal is unmuted.Type: GrantFiled: September 15, 2017Date of Patent: September 24, 2019Assignee: Cirrus Logic, Inc.Inventors: Shafagh Kamkar, Bruce Duewer, Dylan Hester
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Patent number: 10418044Abstract: A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.Type: GrantFiled: September 15, 2017Date of Patent: September 17, 2019Assignee: Cirrus Logic, Inc.Inventors: Shafagh Kamkar, Dylan Hester, Bruce Duewer
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Publication number: 20180218744Abstract: An audio processing circuit may have a first path for processing multi-bit audio signals in parallel with a second path for processing single-bit audio signals. The parallel paths may share a common input node for receiving audio data and a common output node for reproducing audio at a transducer. Each path may have a volume control for adjusting an output of the path. The audio processing circuit may determine a type of an audio signal received at the input. The path not corresponding to the detected type of the audio signal is muted, and the path corresponding to the detected type of audio signal is unmuted.Type: ApplicationFiled: September 15, 2017Publication date: August 2, 2018Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Shafagh Kamkar, Bruce Duewer, Dylan Hester
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Publication number: 20180217807Abstract: Audio content in a single-bit audio stream can be reproduced at a transducer by mapping the single-bit audio stream to symbols in a multi-bit audio stream. Volume control may be implemented, in part, in the digital domain and, in part, in the analog domain. In the digital domain, when converting the single-bit audio stream to a plurality of symbols, the plurality of symbols is selected based, at least in part, on audio content of the single-bit audio stream and a desired volume level. In the analog domain, when converting an analog current signal output from a current-steering DAC processing the plurality of symbols to an analog voltage signal, an analog gain value may be selected based, at least in part, on the desired volume level.Type: ApplicationFiled: September 15, 2017Publication date: August 2, 2018Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Bruce Duewer, Dylan Hester, Shafagh Kamkar
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Publication number: 20180218745Abstract: A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.Type: ApplicationFiled: September 15, 2017Publication date: August 2, 2018Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Shafagh Kamkar, Dylan Hester, Bruce Duewer
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Patent number: 8581756Abstract: A digital signal processing circuit, such as a digital-to-analog converter (DAC) having multiple cascaded processing stages, some of which are selectably placed in a low-power non-operating state according to a lower-power operating mode of the digital signal processing circuit and are placed in an operating state according to another higher-performance operating mode of the circuit. The output sample rates of the stages differ, so that the sample rate through the cascade changes. A signal characteristic determination block generates an indication of one or both of an amplitude and/or frequency of the input signal, so that the operating mode of the digital signal processing circuit is selected in conformity with the indication of amplitude and/or frequency of the input signal.Type: GrantFiled: September 27, 2012Date of Patent: November 12, 2013Assignee: Cirrus Logic, Inc.Inventors: Bruce Duewer, Gautham Devendra Kamath
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Patent number: 7345514Abstract: An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is an internal reference voltage pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset and wherein the internal reference voltage pin is normally used by the integrated circuit for internally generating a reference voltage.Type: GrantFiled: February 24, 2006Date of Patent: March 18, 2008Assignee: Cirrus Logic, Inc.Inventor: Bruce Duewer
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Patent number: 7283076Abstract: A method and apparatus for implementing non-integer sample hold operations in a sigma-delta digital-to-analog converter system includes an interpolation filter, a polyphase filter circuit, and a modulator. The polyphase filter circuit is used to virtual upsample a digital input signal by a predetermined non-integer upsample ratio of a relatively large number. The polyphase filter circuit is formed of a long zero-order hold and a short FIR filter so that only several branches associated with the polyphase filter circuit corresponding to output samples immediately after a transition of the digital input signal is required to be calculated, thereby reducing the need to store a large number of filter coefficients and eliminating complex computations.Type: GrantFiled: June 29, 2006Date of Patent: October 16, 2007Assignee: Cirrus Logic, Inc.Inventors: Lei Ding, John L. Melanson, Xaiofan Fei, Bruce Duewer
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Publication number: 20060238229Abstract: An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is an internal reference voltage pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset and wherein the internal reference voltage pin is normally used by the integrated circuit for internally generating a reference voltage.Type: ApplicationFiled: February 24, 2006Publication date: October 26, 2006Inventor: Bruce Duewer
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Patent number: 7034593Abstract: An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is a non-dedicated reset pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset.Type: GrantFiled: November 13, 2003Date of Patent: April 25, 2006Assignee: Cirrus Logic, Inc.Inventor: Bruce Duewer
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Patent number: 6965335Abstract: A method of performing digital to analog conversion includes generating a pulse width modulated data stream and another pulse width modulated data stream, encoding patterns of the pulse width modulated data stream selected to minimize distortion in the another pulse width modulated stream caused by edges in the pulse width modulated data stream. The pulse width modulated data stream and the another pulse width modulated data stream are converted into an analog signal and another analog signal converting in corresponding digital to analog conversion elements and the analog signal and the another analog signal are summed to generate an analog output signal.Type: GrantFiled: January 27, 2004Date of Patent: November 15, 2005Assignee: Cirrus Logic, Inc.Inventors: Brian David Trotter, Bruce Duewer, John Laurence Melanson
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Publication number: 20050093727Abstract: A method of operating a delta-sigma modulator by providing a variable-level quantizer, which selectively enables an additional quantizer level(s) during a ramp up sequence of the modulator. The additional quantizer level(s) is/are disabled during normal operation. The quantizer truncates a summer output and selectively enables the additional quantizer levels by clipping the truncated sum within a first range of quantizer levels during the ramp up sequence and within a second range of quantizer levels during normal operation in which there are more quantizer levels in the first range than in the second range. The quantizer preferably enables at least two additional quantizer levels at a low end of the quantizer range. For example, the range of quantizer levels for normal operation of the modulator can be from ?6 to +6, while the range of quantizer levels for ramp up operation of the modulator can be from ?8 to +7.Type: ApplicationFiled: October 31, 2003Publication date: May 5, 2005Inventors: Brian Trotter, Bruce Duewer
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Patent number: 6885330Abstract: A pulse width modulator includes at least one input for receiving an input signal and pulse width modulation circuitry for generating a pulse width modulated stream and another pulse width modulated stream. The pulse width modulated stream and the another pulse width modulated stream are nominally out of phase and together represent the received input signal. A summer sums the pulse width modulated stream and the another pulse width modulated stream to generate an analog output signal.Type: GrantFiled: September 5, 2003Date of Patent: April 26, 2005Assignee: Cirrus Logic, Inc.Inventors: Brian David Trotter, Bruce Duewer, John Laurence Melanson
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Publication number: 20050052304Abstract: A pulse width modulator includes at least one input for receiving an input signal and pulse width modulation circuitry for generating a pulse width modulated stream and another pulse width modulated stream. The pulse width modulated stream and the another pulse width modulated stream are nominally out of phase and together represent the received input signal. A summer sums the pulse width modulated stream and the another pulse width modulated stream to generate an analog output signal.Type: ApplicationFiled: September 5, 2003Publication date: March 10, 2005Applicant: Cirrus Logic, IncInventors: Brian Trotter, Bruce Duewer, John Melanson
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Publication number: 20050010399Abstract: A method of controlling a terminal of an integrated circuit includes determining a frequency ratio between a frequency of a signal and a frequency of another signal received by an integrated circuit. A selected signal appearing at a selected terminal of the integrated circuit is selectively interpreted in accordance with an operating mode when the frequency ratio is below a selected value and in accordance with another operating mode when the frequency of the signal is above a selected value.Type: ApplicationFiled: June 17, 2003Publication date: January 13, 2005Applicant: Cirrus Logic, Inc.Inventor: Bruce Duewer