Abstract: A structure connecting superconductor transmission lines to integrated circuits comprises a plurality of interconnection substrates having superconducting transmission path deposited thereon in contact with metallic contact areas, and integrated circuit chip carrier substrates for mounting integrated circuits and having metallic contact areas. The substrates are mounted in a retainer structure and are separated by spacers which have apertures in registration with the contact areas. Contact devices are selectively inserted in the apertures to establish an interconnection pattern between the substrates. The retainer structure applies force to the substrates to assure physical contact between the substrates and the contact device. The structure may be assembled and disassembled for replacement of parts or reconfiguration of interconnections, without the application of heat or other processes which are incompatible with relatively brittle and heat sensitive superconducting materials.

Abstract: An electronic system having components operating at low temperature at various locations within the system, cryogenic fluid and electrical power are distributed by means of the same conduit. In one embodiment, the conduit consists of a supply section and a return section with each section comprising a channel for conveying cryogenic fluid having superconducing walls for conveying electrical power. In another embodiment of the invention, the conduit comprises a copper rod having channels formed therein for the transport of cryogenic fluid and a channel for supporting a rod of superconducing material therein. The superconducing rod conducts electrical current to a subsystem while being cooled by cryogenic fluid in nearby channels and the cryogenic fluid is used at its destination for cooling purposes.

Abstract: A switching array comprising low power switching elements for switching high bandwidth pulse encoded signals with minimum distortion. Each switching element comprises an emitter-coupled pair of transistors which are used to switch the pulse encoded signals. The pair of transistors are enabled and disabled by inhibiting the flow of electrical current through the latter. A transistorized switch controls the electrical current in the pair of transistors in response to signals from a control register within the switching array. Since no current is flowing in the pair of transistors when the element is inhibited, the power dissipation approaches zero in the inhibit state resulting in an overall low power dissipation for the switching array since only a small number of elements are normally enabled at any time.

Abstract: A time division multiplex (TDM) switching network is disclosed in which at least part of the network comprises a space switching portion (TMS) and in which the need for duplication of the space switching portion, and like methods of achieving network reliability, is eliminated. Data from an incoming channel is partitioned into successive blocks, a prescribed number of which form a set of blocks. The blocks are of predetermined size. Each of the blocks of a set is switched via different paths of the space portion of the network. A single network fault can therefore cause the loss of only one block of data in a set. This loss can be made insignificant in the case of data representing telephone conversations. For data not representing telephone conversations, error checking and correcting information is added to the set before transmission through the space portion of the network and errors occurring during transmission are corrected thereafter.

Abstract: An adder circuit for generating a completion signal indicating the completion of adder operation. A detector circuit (103) is connected to the power supply bus (102) of a multistage parallel adder for detecting voltage variations caused by the operation of the adder stages and for generating a completion signal when these voltage variations have ceased to occur for a predetermined period of time.