Abstract: In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information.

Abstract: In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information.

Abstract: In order to efficiently recover from a processing error in a central processing trait (CPU) incorporating a cache memory and a basic processing unit, the BPU is provided in duplicate, and all BPU data manipulation operations are performed redundantly. After duplicate data has been obtained from the cache memory and manipulated by the duplicate BPUs, the outputs from the duplicate BPUs are placed on respective master (MRB) and slave (SRB) result busses which are coupled to the cache unit where the results are compared for identity. If the results are not identical, a local error signal is issued.

Abstract: In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.

Abstract: In a Central Processing Unit (CPU) incorporating a Basic Processing Unit (BPU) which includes an address and execution (AX) unit, a decimal numeric (DN) unit and a floating point (FP) unit and also incorporating a cache unit situated logically intermediate the BPU and system memory, BPU data manipulation errors are sensed by duplicating each of the AX, DN and FP chips (i.e., duplicating the BPU) and performing all BPU data manipulation operations redundantly. The outputs from the duplicate BPUs are placed on respective master (MRB) and slave (SRB) result busses which are coupled to the cache unit, and the results are compared, byte-by-byte in the cache unit. If the results are not identical in each byte of the result, the individual chip handling the byte in the cache unit and detecting the no-compare condition issues an individual error signal, and appropriate steps to remedy or otherwise respond to the error signal may be undertaken within the cache unit, within the CPU and within the system.