Patents by Inventor Bruce E. Pederson

Bruce E. Pederson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9800001
    Abstract: Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventors: James E. Jaussi, Stephen R. Mooney, Howard L. Heck, Bruce E. Pederson, Bryan K. Casper
  • Publication number: 20160352055
    Abstract: Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
    Type: Application
    Filed: May 11, 2016
    Publication date: December 1, 2016
    Inventors: James E. Jaussi, Stephen R. Mooney, Howard L. Heck, Bruce E. Pederson, Bryan K. Casper
  • Patent number: 9362684
    Abstract: Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: James E. Jaussi, Stephen R. Mooney, Howard L. Heck, Bruce E. Pederson, Bryan K. Casper
  • Patent number: 9106217
    Abstract: Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: James E. Jaussi, Bruce E. Pederson, Howard L. Heck, Stephen R. Mooney
  • Publication number: 20140357128
    Abstract: Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
    Type: Application
    Filed: December 14, 2011
    Publication date: December 4, 2014
    Inventors: James E. Jaussi, Stephen R. Mooney, Howard L. Heck, Bruce E. Pederson, Bryan K. Casper
  • Publication number: 20140184270
    Abstract: Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.
    Type: Application
    Filed: December 6, 2011
    Publication date: July 3, 2014
    Inventors: James E. Jaussi, Bruce E. Pederson, Howard L. Heck, Stephen R. Mooney