Abstract: Compact and efficient hardware architectures for implementing lifting-based DWTs, including 1-D and 2-D versions of recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a 5-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array.

Abstract: Compact and efficient hardware architectures for implementing lifting-based DWTs, including 1-D and 2-D versions of recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a 5-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array.

Abstract: A method and apparatus for classifying signals into a multiplicity of signal classes which employs discriminant functions of low-complexity discriminant variables that are computed directly from the passband signal. The method can be applied to the problem of classifying voiceband data (VBD), facsimile (FAX), native binary data, and speech on a 64 Kbps digital channel. In a hybrid two stage classification system, the first stage employs linear discriminant functions to make classification decisions into a smaller number of possible preliminary signal classes. The decisions of the first stage are then refined by a second stage that uses nonlinear discriminant functions such as quadratic or pseudo-quadratic functions. The second stage of a hybrid classifier then assigns the signal into a larger number of possible classes than does the first stage of the classifier alone.

Abstract: A dynamic random access memory for storing one of N levels in each of a plurality of memory cells, the memory cells having storage capacitors coupled to bitline pairs through switches for writing and reading data to and from the memory cells, the memory comprising: at least N−1 bitline pairs, each bitline pair being divided into N−1 sub-bitlines by first switches therebetween; the sub-bitline pairs of each bitline being coupled to adjacent sub-bitline pairs by second switches therebetween, to form N−1 groups of sub-bitlines each for producing one of N−1 reference voltages; sense amplifiers coupled to each sub-bitline pair; N−1 sub-bitline pairs each having reference cells for selective coupling thereto; (N−2)(N−1) sub-bitline pairs each having generate cells for selective coupling thereto; and sub-bitline pairs being selectively connected in a group through switches such that: the sub-bitlines in the group are precharged to one of a plurality of voltages; one of the (

Abstract: A dynamic random access memory for storing one of N levels in each of a plurality of memory cells, the memory cells having storage capacitors coupled to bitline pairs through switches for writing and reading data to and from the memory cells, the memory comprising: at least N−1 bitline pairs, each bitline pair being divided into N−1 sub-bitlines by first switches therebetween; the sub-bitline pairs of each bitline being coupled to adjacent sub-bitline pairs by second switches therebetween, to form N−1 groups of sub-bitlines each for producing one of N−1 reference voltages; sense amplifiers coupled to each sub-bitline pair; N−1 sub-bitline pairs each having reference cells for selective coupling thereto; (N−2)(N−1) sub-bitline pairs each having generate cells for selective coupling thereto; and sub-bitline pairs being selectively connected in a group through switches such that: the sub-bitlines in the group are precharged to one of a plurality of voltages; one of the (

Abstract: A method of testing a random access memory (RAM) for single V-coupling faults by establishing a first current value for each cell, for each cell and for each of m data backgrounds, generating a data bit corresponding to an element of an (n, V-1)-exhaustive matrix, and for each of m data backgrounds: (1) applying a read write sequence to each cell; and (2) for each background except the mth background, updating the current value of all cells according to the data bits corresponding to that cell; reading each cell of the RAM; and discarding or repairing the RAM if a cell coupling fault is apparent from the series of values read from the cells of the RAM. Data bits are generated by a matrix reconstruction method or a pseudo-random generator using a hashing of the address of the cell to which the data bit is to be applied.