Abstract: A data processing system, and a method of operating a data processing system. The data processing system comprises a clock generator for generating a system clock signal, and a memory unit having a plurality of memory modules for storing data. The data processing system further comprises a memory controller coupled to the clock generator for receiving the system clock signal therefrom, and coupled to the memory modules for outputting memory address and control signals to said modules. The memory controller is programmable to have different clock-to-output delays, on signals from the memory controller end, based on the memory installed in the system.

Abstract: A memory module configured such that it can be operated as a first memory module such as a (Single In-line Memory Module) SIMM or as a second memory module such as a (Dual In-linc Memory Module) DIMM module without requiring external switching circuitry. This is accomplished by providing a memory module card with a circuit thereon that is designed to emulate a DIMM module when plugged into a DIMM socket as found in the latest computer architectures and to emulate a SIMM module when plugged into a SIMM socket as found in older computer architectures. The memory module is provided with memory devices (DRAMS or SDRAMS) and interconnecting bypass devices (CMOS transistor pairs) mounted thereon.

Abstract: A printed circuit card having first and second circuit units mounted thereon in connection to terminal pads adjacent two card edges, with the first and second circuit units being in connection to each other and to select pads of a first edge such that upon insertion of that edge into a given card socket, both circuit units are enabled, and the circuit units also being in connection to the pads of a second edge such that upon insertion of that edge into a second card socket, only the second circuit unit is enabled. In the preferred embodiment, the card is a memory module card having buffer and memory circuit units designed to cooperate with each other and with either of standard, buffered or unbuffered memory card sockets in a system board in accordance with insertion of a first or second pad edge in one of the card sockets to automatically provide, either combined circuit unit operation, or single circuit operation. The invention is also applicable to clocked register circuits and series pass devices.

Abstract: A dynamically configurable memory adapter is provided for configuring SIMMs in a computer system which employs DIMMs. The adapter includes a plurality of SIMM sockets, a programmable logic device, an EEPROM, a bus controller, and DIP switches. The programmable logic device includes logic for interrogating and configuring serial presence detect data based on a plurality of SIMM characteristics included therein. The serial presence detect data is read by the computer system memory controller during the boot-up process. The dynamically configurable memory adapter also includes direct wiring between the DIMM interface and the SIMMs to thereby allow the SIMMs to directly talk to the memory controller.

Abstract: The signal configuration for addressable DRAMs from a system is changed from a signal that actuates a single bank of DRAMs having Y/X row/column addresses actuated by a single RAS, to a signal configuration that provides two RAS signals for two banks of DRAMs having Y-1/X row/column addresses actuated by two RAS signals. This is done by converting the high order address bit from the system to a RAS signal actuated by a system RAS when, and only when, the high order bit is of a given value.

Abstract: A method and logic circuit are provided which method and logic circuit allow both a CBR and hidden refresh to take place on DRAM's populating SIMM's or DIMM's, wherein both a single system RAS and single system CAS are converted to multiple RAS's and multiple CAS's for normal read/write operation on the DRAM's.