Abstract: A dual port enclosure monitor for servicing a dual port bus includes four primary components: two enclosure monitors and two bus expanders with isolation circuitry. The sub-system is configured such that an enclosure monitor and an expander are both connected to an external port. The internal bus then connects the two expanders, as well as all of the internal devices (e.g. hard drives, CD-ROMs, tape drives). The enclosure monitors can communicate with various host devices over the external buses. These host devices can instruct the enclosure monitor to either connect or isolate the internal bus, thereby the peripherals attached to it. This is accomplished through a set of independent control signals that run between the monitor and the expander. There are three different methods of control. The first is independent, paired control between enclosure monitor/bus expander pairs. A separate host controls each enclosure monitor/bus expander pair.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory (“DRAM”) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (“ZBT”), or pipeline burst static random access memory (“SRAM”) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory ("DRAM") device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround ("ZBT"), or pipeline burst static random access memory ("SRAM") devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a "Wait" pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater.