Abstract: A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region where virtual addresses are not unique. A probe receives trace information from the processor. A host system receives the trace information from the probe. The host system includes a data structure associating a process name, a process identification and a set of instruction counters. Each instruction counter is incremented upon the processing of a designated virtual address within the trace information. A profiling module processes information associated with the process name and set of instruction counters to identify a performance problem in the application.

Abstract: A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region where virtual addresses are not unique. A probe receives trace information from the processor. A host system receives the trace information from the probe. The host system includes a data structure associating a process name, a process identification and a set of instruction counters. Each instruction counter is incremented upon the processing of a designated virtual address within the trace information. A profiling module processes information associated with the process name and set of instruction counters to identify a performance problem in the application.

Abstract: A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism.

Abstract: A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism.

Abstract: A system includes a processor to generate a free-running trace stream and a probe with a real-time decoder to dynamically detect a trigger included in the free-running trace stream.

Abstract: A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism.

Abstract: A software analysis system for acquiring, storing, and analyzing certain predetermined characteristics of a computer program includes a method and apparatus for acquiring certain lines of high-level language instruction code without the need for statistical sampling. Each line of instruction code generates at least one address in assembly language which is encoded with a tag and stored in a first-in, first-out memory. The memory output is asynchronous with its output such that tagged addresses are stored in real time but extracted from memory at a predetermined rate. This allows the system to acquire all software event of interest. Each tagged address is also marked with a time stamp so that the time between acquisition of each of the software events of interest may be analyzed to determine, for example, the length of time spent in a particular subroutine.

Abstract: An apparatus and method which may be used with a logic analyzer are provided for acquiring groups of data words from the circuitry of a synchronous logic system where each group contains a qualified data word together with a predetermined number of data words which have preceded it. The apparatus includes a circuit for detecting the qualified word and a data storage device having a plurality of separately-addressable storage locations. Both the qualified data detector and the storage device are logically connected to the synchronous logic circuitry. The apparatus further includes an addressing circuit which responds to the detection of a qualified word and to the presence of data words on the synchronous logic circuitry by producing storage addresses which are provided to the storage device for storing the data word groups in successive storage locations.