Abstract: A hybrid fiber/coax digital data transmission system in which data from a plurality of subscribers are transmitted upstream to a headend demodulator in a series of data bursts. The headend demodulator acquires and synchronizes a data burst by detecting a BPSK preamble having a repetitive one and zero pattern (10101010101000). The pattern is detected by integrating clock energy in an envelope of a preamble length transmission and using the last three symbols (0,0,0) as a frame marker after differential decoding. Noise in the system is periodically measured by detecting an empty burst placed periodically in the data stream. A first-in, first-out (FIFO) memory allows closer spacing for the data bursts by permitting asynchronous received and output clocks.

Abstract: A time division multiple access (TDMA) burst receiver and a method for recognizing and providing a time-of-arrival of a TDMA burst transmission having a selected preamble. The TDMA burst receiver includes a blanker for blanking the TDMA burst transmission when the signal level exceeds a pre-selected noise threshold, a signal threshold detector for providing a first tentative time-of-arrival when a correlation of the TDMA burst transmission and the selected preamble exceeds a first threshold and a second tentative time-of-arrival only when the correlation exceeds a second threshold within a selected time period following the first tentative time-of-arrival, and a state machine for providing an operational time-of-arrival corresponding to the first tentative time-of-arrival when the second tentative time-of-arrival is not received and the second tentative time-of-arrival when the second time-of-arrival is received.

Abstract: An adaptive filter or equalizer for digital data communication includes, a first cascade circuit connected to operate as a digital finite impulse response (FIR) filter, the first cascade circuit having a first plurality of input taps for application of filter weighting signals thereto, a single input for samples of input data, and an output for filtered data. A second cascade circuit, which has the inverse canonical form, has a second plurality of input taps for receiving signal samples of input data, a single input for receiving error signals, and an output for yielding a succession of weighting signals. A sequencing circuit applies data signals to successive cascade stages of the second cascade circuit in a time sequence which is the reverse of that of the weight signals applied to the plurality of input taps of the first cascade circuit, such that the second cascade circuit functions as a weighting signal generator for the first cascade circuit.