Abstract: A grid array assembly is provided employing a thin copper or steel carrier frame having apertures extending longitudinally of the frame. A series of semi-flexible substrate printed circuit boards are mounted in seriatim to peripheral edges of the apertures, the circuit boards including bonding pads and metallization on a first surface and conductive vias in the circuit boards extending to a second opposite surface containing a contact pad array. The carrier strip with the mounted circuit boards are passed to a station where an IC die is mounted on the board first surface, wire bonds are placed from the die to the bonding pads and the assembly encapsulated using a portion of the carrier strip as a mold gate to form a package body. Subsequently each grid array assembly is singulated from the carrier strip.

Abstract: A grid array assembly method and apparatus uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surfaces wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.

Abstract: A grid array assembly method uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes or vias in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surface, wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.

Abstract: A grid array assembly method and apparatus uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surface, wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.

Abstract: A grid array assembly method uses a semi-flexible substrate printed circuit board and includes steps of providing a series of conforming boards each board including bonding pads and metallization on a first surface and conductive vias in the board extending to a second opposite surface containing a contact pad array, testing the boards and determining acceptable boards. A carrier strip with longitudinally aligned apertures mounts individual accepted boards. The strip with mounted boards is passed to a station where an IC die is mounted on the board first surface, wire bonds are placed from the die to the bonding pads and the assembly encapsulated by automolding against a board first surface portion using the strip as the mold gate to form a package body. Subsequently interconnecting balls or bumps are placed on the contact pads and the assembly is removed from the strip.

Abstract: According to the invention, an electronic device mounted on a substrate is encapsulated using a standard two-piece mold. A novel degating region is formed on a surface of the substrate to allow removal of excess encapsulant formed on the surface during molding without damaging the remainder of the device. The material of the degating region that contacts the encapsulant forms a weak bond with the encapsulant, relative to the bond formed between the encapsulant and the substrate, so that the encapsulant can be peeled away from the degating region without damaging the substrate or other portion of the device. The degating region is provided without introducing additional steps into the process for forming the device. The presence of the degating region eliminates the necessity of using a three-piece or modified two-piece mold to achieve top gating in order to degate without damaging the device. In one embodiment, the degating region is made of gold.

Abstract: An integrated circuit package includes a stacked integrated circuit chip arrangement (140) placed on a circuit substrate. The stacked IC chip arrangement includes a first IC chip (110) and a second IC chip (120), each having an array of terminals (116, 126) and being positioned in a face-to-face manner. An interposed substrate (130) is positioned between the first IC chip (110) and the second IC chip (120) such that circuitry disposed on the interposed substrate (130) provides electrical connection among the arrays of terminals of the first IC chip (110) and the second IC chip (120) and external circuitry.

Abstract: An integrated circuit package (10) comprises a semiconductor die (14) having a top surface and a bottom surface, and a substrate (16) for receiving the semiconductor die. The substrate should have an aperture(s) (18) below the semiconductor die for providing moisture relief during temperature excursions. An adhesive (20) applied to the substrate allows for mounting the semiconductor die to the substrate. Then, the semiconductor die is wirebonded to the substrate. Finally, an encapsulant (12) for sealing the top surface of the semiconductor die is formed over the semiconductor die and portions of the substrate.

Abstract: A leadless pad array chip carrier package is disclosed, employing a printed circuit board (22) having an array of solder pads (34) on the bottom side. A semiconductor device (24) is electrically wire bonded (49) and attached with conductive adhesive (47) to the metallization patterns (43, 25) of the printed circuit board (22). A protective plastic cover (26) is transfer molded about the semiconductor device (24) covering substantially all of the top side of the printed circuit board (22).

Abstract: A method of making a pad array chip carrier package is disclosed. A semiconductor device (10) is bonded to a ceramic substrate (12). The semiconductor device may be attached to the substrate by wirebonding, tab bonding or flip chip bonding. The bonded assembly (16) is then attached to a flexible temporary support substrate (18) by means of an adhesive (19). The entire assembly is then placed into a mold cavity (20 and 22) and registered against the temporary support substrate (18). Plastic material (30) is molded about the semiconductor device and associated wirebonds in order to encapsulate the device. After removal from the mold, the encapsulated assembly is removed from the temporary support substrate (18) by peeling the temporary support substrate (18) from the circuit substrate.

Abstract: A shielded semiconductor package and a method for manufacturing the package is provided. The shielded semiconductor package comprises a substrate (10) having a metallization pattern (12, 13), with one portion of the metallization pattern being a circuit ground (13). A semiconductor device (16) is electrically interconnected (17) to the metallization pattern (12). A perforated metal shield or screen (18) covers the semiconductor device (16) and is electrically and mechanically attached to the metallization circuit ground (13) in order to shield the semiconductor device (16) from radio frequency energy. A resin material (14) is transfer molded about the semiconductor device, the electrical interconnections, and the metal screen to form the completed package.

Abstract: An overmolded semiconductor package (150) is formed by electrically and mechanically attaching a semiconductor device (100) to a substrate (110) having at least one hole (130). A plastic molding compound (140) is overmolded around the semiconductor device 100) so as to encapsulate the device, the molding compound (140) extending at least partially into the substrate hole (130) to form an anchor (135) to aid in bonding the molding compound to the substrate. An alternate embodiment of the invention forms a pedestal (449) from the portion of the molding compound extending beyond the surface of the substrate. The pedestal functions as an anchor to aid in bonding the molding compound (440) to the substrate, and also as a spacer to maintain a preselected clearance between the substrate (410) and the printed circuit board (460). The portion of the molding compound extending beyond the surface of the substrate may also be used to form an alignment pin (548).

Abstract: A flexible film is made into a substrate (100) having metallization patterns. A semiconductor device (106) is affixed to the substrate, and the assembly is heated to expand the substrate. A cover (110) is attached to the substrate, over the device (106). Upon cooling, the substrate (100) shrinks and becomes taut and planar within the reinforced area. Alternatively, a reinforcing ring (210) can be attached to the substrate (200) either before or after attachment of the semiconductor device (206).

Abstract: A die pad (108) with a punched hole providing a throughway (110) is affixed upon the chip carrier base 100. Such throughway permits the electronic interconnection of the die backside (112) to a conductive runner (104) by electrically conductive material (110) set between the die backside (112) and the conductive runner (104).

Abstract: A method of manufacturing a chip carrier from a universal ceramic substrate provides for a universal ceramic substrate having first and second opposed sides and an array of conductively filled through-holes. On the first side, wire bond pads and conductors connected to the conductively filled through-holes are provided as required. Similarly, on the second side, solder pads on the conductively filled through-holes are provided as required. Finally, at least one insulating layer is provided over part of the first side for die attachment.

Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.

Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.