Abstract: Bus logic couples plural master logic units with plural slave logic units to enable data transfers. Each master unit performs an address transfer which, when received by a specified slave unit, causes a data transfer between that master unit and said specified slave unit. Each slave unit must complete a data transfer prior to performing any further data transfers. A slave unit performs data transfers in an order which differs from that in which associated address transfers were received by that slave unit. In response to an adress transfer, the bus logic couples a master unit with a slave unit to enable a data transfer. The bus logic determines whether propagation of an address transfer may cause a deadlock situation where data transfers can not take place between affected master and slave units and, if so, to prevent propagating that address transfer.