Abstract: Hot restart of a hypervisor by replacing a running first hypervisor by a second hypervisor with minimally perceptible downtime to guest partitions. A first hypervisor is executed on a computing system. The first hypervisor is configured to create one or more guest partitions. During the hot restart, a service partition is generated and initialized with a second hypervisor. At least a portion of runtime state of the first hypervisor is migrated and synchronized to the second hypervisor using inverse hypercalls. After the synchronization, the second hypervisor is devirtualized from the service partition to replace the first hypervisor. Devirtualizing includes transferring control of hardware resources from the first hypervisor to the second hypervisor, using the previously migrated and synchronized runtime state.

Abstract: Examples of the present disclosure describe systems and methods for CPU core off-parking. In one example implementation, a performance test is executed for a CPU core that is part of a first mapping of virtual processors to logical CPU cores. A set of performance indicators is received for the CPU core. Based on the set of performance indicators, a determination is made regarding whether to off-park the CPU core. If it is determined that the CPU core is to be off-parked, a second mapping of virtual processors to logical CPU cores is created, where the CPU core to be off-parked is not part of the second mapping. The second mapping is then implemented.

Abstract: Isolating resources of a virtual machine (VM) guest from a host operating system. A computer system receives an acceptance request from a guest partition corresponding to an isolated VM. The acceptance request identifies a guest memory page that is mapped into a guest physical address space of the guest partition, and a memory page visibility class. The computer system determines whether a physical memory page that is mapped to the guest memory page meets the memory page visibility class. The computer system sets a page acceptance indication for the guest memory page from an unaccepted state to an accepted state based on the physical memory page meeting the memory page visibility class.

Abstract: Hot restart of a hypervisor by replacing a running first hypervisor by a second hypervisor with minimally perceptible downtime to guest partitions. A first hypervisor is executed on a computing system. The first hypervisor is configured to create one or more guest partitions. During the hot restart, a service partition is generated and initialized with a second hypervisor. At least a portion of runtime state of the first hypervisor is migrated and synchronized to the second hypervisor using inverse hypercalls. After the synchronization, the second hypervisor is devirtualized from the service partition to replace the first hypervisor. Devirtualizing includes transferring control of hardware resources from the first hypervisor to the second hypervisor, using the previously migrated and synchronized runtime state.

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how interrupts may be provided to targeted virtual processors, regardless of where the virtual processors are currently executing. That is, when an interrupt is received, the interrupt may be delivered to a specified virtual processor regardless of which logical processor is currently hosting the virtual processor.

Abstract: A processor supporting a translation lookaside buffer (TLB) modification instruction for updating a hardware-managed TLB is disclosed. A page table (PT) entry (PTE) corresponding to a virtual memory address is identified by a PT walking circuit walking the PT and a corresponding TLB entry is created. An execution circuit in the processor executes a TLB modification instruction to cause the TLB entry corresponding to the virtual memory address to be updated based on an update to the PT mapping information in the PTE corresponding to the virtual memory address. In one example, a portion of the PT mapping information in a PTE corresponding to a virtual memory address is stored in a TLB mapping information in a TLB entry corresponding to the virtual memory address in response to the TLB modification instruction being executed by the execution circuit without invalidating the TLB entry.

Abstract: Hot restart of a hypervisor by replacing a running first hypervisor by a second hypervisor with minimally perceptible downtime to guest partitions. A first hypervisor is executed on a computing system. The first hypervisor is configured to create one or more guest partitions. During the hot restart, a service partition is generated and initialized with a second hypervisor. At least a portion of runtime state of the first hypervisor is migrated and synchronized to the second hypervisor using inverse hypercalls. After the synchronization, the second hypervisor is devirtualized from the service partition to replace the first hypervisor. Devirtualizing includes transferring control of hardware resources from the first hypervisor to the second hypervisor, using the previously migrated and synchronized runtime state.

Abstract: The disclosed technology is generally directed to virtualization technology. The disclosed technology includes providing processor feature ID information requested by, or from, a virtual machine (VM), virtualized application, Virtualization Based Security (VBS) user mode process, VBS kernel mode process, or other guest partition, by a processor. Such information may be provided based on information provided a priori to the processor, for example, by a supervisory partition, such as a hypervisor. The disclosed technology also includes a supervisory partition, for example, that provides such information to the processor, and includes guest partitions that receive such information.

Abstract: Hot restart of a hypervisor by replacing a running first hypervisor by a second hypervisor with minimally perceptible downtime to guest partitions. A first hypervisor is executed on a computing system. The first hypervisor is configured to create one or more guest partitions. During the hot restart, a service partition is generated and initialized with a second hypervisor. At least a portion of runtime state of the first hypervisor is migrated and synchronized to the second hypervisor using inverse hypercalls. After the synchronization, the second hypervisor is devirtualized from the service partition to replace the first hypervisor. Devirtualizing includes transferring control of hardware resources from the first hypervisor to the second hypervisor, using the previously migrated and synchronized runtime state.

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how a hypervisor of a host machine may monitor the status of one or more virtual processors that are executing on the host machine and deliver interrupts to the virtual processors based on a number of factors including, but not limited to, a priority of the interrupt, a priority of the virtual processor, a current workload of the virtual processor and so on.

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how a hypervisor of a host machine may monitor the status of one or more virtual processors that are executing on the host machine and deliver interrupts to the virtual processors based on a number of factors including, but not limited to, a priority of the interrupt, a priority of the virtual processor, a current workload of the virtual processor and so on.

Abstract: The disclosed technology is generally directed to virtualization technology. The disclosed technology includes providing processor feature ID information requested by, or from, a virtual machine (VM), virtualized application, Virtualization Based Security (VBS) user mode process, VBS kernel mode process, or other guest partition, by a processor. Such information may be provided based on information provided a priori to the processor, for example, by a supervisory partition, such as a hypervisor. The disclosed technology also includes a supervisory partition, for example, that provides such information to the processor, and includes guest partitions that receive such information.

Abstract: This disclosure generally relates to time and timer techniques that may be used to virtualize one or more virtual machines. In an example, it may be possible to save and restore a timer of a virtual machine while preserving timer information associated with the timer (e.g., an expiration time, whether the most recent expiration has been signaled, and the enable bit, etc.). For example, a first mode may enable restoring a timer based on a previously-existing enable bit, thereby retaining the state of the timer (e.g., whether the timer is programmed to fire and/or whether the most recent expiration has been signaled). By contrast, a second mode of setting a timer may automatically set the enable bit, thereby automatically enabling the timer to fire, as may be expected by a virtual machine when setting a timer.

Abstract: The disclosed technology is generally directed to the patching of executing binaries. In one example of the technology, at separate times, a plurality of hot patch requests is received. Each hot patch request of the plurality of hot patch requests includes a corresponding hot patch to hot patch the executing binary. A cardinality of the plurality of hot patch requested is greater than the fixed number of logical patch slots. with the executing binary continuing to execute, each time a request to apply a hot patch to the executing binary is received, the corresponding hot patch is assigned to an inactive logical patch slot of the fixed number of logical patch slots. The corresponding hot patch is executed from the assigned logical patch slot to hot patch the executing binary based on the corresponding hot patch.

Abstract: This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.

Abstract: This disclosure generally relates to hypervisor memory virtualization. In an example, multiple page table stages may be used to provide a page table that may be used by a processor when processing a workload for a nested virtual machine. An intermediate (e.g., nested) hypervisor may request an additional page table stage from a parent hypervisor, which may be used to virtualize memory for one or more nested virtual machines managed by the intermediate hypervisor. Accordingly, a processor may use the additional page table stages to ultimately translate a virtual memory address for a nested virtual machine to a physical memory address.

Abstract: The disclosed technology is generally directed to the patching of executing binaries. In one example of the technology, at separate times, a plurality of hot patch requests is received. Each hot patch request of the plurality of hot patch requests includes a corresponding hot patch to hot patch the executing binary. A cardinality of the plurality of hot patch requested is greater than the fixed number of logical patch slots. with the executing binary continuing to execute, each time a request to apply a hot patch to the executing binary is received, the corresponding hot patch is assigned to an inactive logical patch slot of the fixed number of logical patch slots. The corresponding hot patch is executed from the assigned logical patch slot to hot patch the executing binary based on the corresponding hot patch.

Abstract: This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.

Abstract: The disclosed technology is generally directed to virtualization technology. The disclosed technology includes providing processor feature ID information requested by, or from, a virtual machine (VM), virtualized application, Virtualization Based Security (VBS) user mode process, VBS kernel mode process, or other guest partition, by a processor. Such information may be provided based on information provided a priori to the processor, for example, by a supervisory partition, such as a hypervisor. The disclosed technology also includes a supervisory partition, for example, that provides such information to the processor, and includes guest partitions that receive such information.

Abstract: This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.