Abstract: Embodiments of the present disclosure describe electrostatic discharge (ESD) circuitry and associated techniques and configurations. In one embodiment, ESD circuitry includes a first node coupled with a supply voltage node and a ground node, a first transistor coupled with the first node and the supply voltage node, a second transistor coupled with the first node and the ground node, a second node coupled with the first transistor and the second transistor, a third transistor coupled with the second node and a third node coupled with the third transistor, wherein a first time period to charge the first node is less than a second time period to discharge the third node. Other embodiments may be described and/or claimed.

Abstract: An operational amplifier includes at least one bias current generator, a first gain stage connected to the at least one bias current generator and defining inputs for the operational amplifier, and a second gain stage. The second gain stage may be connected to the at least one bias current generator. Moreover, the second gain stage may be driven by the first gain stage and define an output for the operational amplifier. The operational amplifier may further include at least one capacitive element connected between the first gain stage and the output. Additionally, a circuit element having a controllable conductance may be connected between the at least one capacitive element and the first gain stage. A control circuit may also be included for controlling the circuit element so that the conductance thereof substantially matches a transconductance of the second gain stage.

Abstract: An operational amplifier includes at least one bias current generator, a first gain stage connected to the at least one bias current generator and defining inputs for the operational amplifier, and a second gain stage. The second gain stage may be connected to the at least one bias current generator. Moreover, the second gain stage may be driven by the first gain stage and define an output for the operational amplifier. The operational amplifier may further include at least one capacitive element connected between the first gain stage and the output. Additionally, a circuit element having a controllable conductance may be connected between the at least one capacitive element and the first gain stage. A control circuit may also be included for controlling the circuit element so that the conductance thereof substantially matches a transconductance of the second gain stage.

Abstract: A digital-to-analog converter (DAC) includes a first array of current source cells extending in first and second transverse directions, and a two-dimensional symmetrical controller for operating current source cells of the first array based upon at least a portion of digital input words and in a symmetrical sequence in both the first and second directions with respect to a medial position of the first array. The medial position preferably defines a centroid for the first array. The two-dimensional symmetrical controller may preferably include a decoder for generating a plurality of control signals based upon predetermined most significant bits (MSBs) of digital input words. Another aspect of the invention relates to the treatment of the LSBs. According to this aspect, the first array further comprises a plurality of second current source cells, and the two-dimensional symmetrical controller further operates the plurality of second current source cells based upon predetermined LSBs of digital input words.

Abstract: A trimmable current cell and method for providing an output current at a desired level which may be used to provide a particular current level for a digital-to-analog converter. The cell includes a first circuit with two fixed resistors connected in series which initially establish the output current, and a second circuit for trimming the output current from the first circuit to the desired level. The second circuit has a series-connected pair of trimmable resistors whose common node is connected to the first circuit at a common node between the fixed resistors. Trimming one of the trimmable resistors increases the output current to the desired level and trimming the other of the trimmable resistors decreases the output current to the desired level.

Abstract: A digital-to-analog converter includes a plurality of current cells, at least one cell in one embodiment including a pair of bipolar current switching transistors connected to a current source and a current summing bus in a current steering configuration so that one transistor is off while the other transistor is on. A temperature compensated control circuit is included for controlling the difference in base-emitter voltages of the bipolar current switching transistors based upon a temperature dependent bias voltage to compensate for a thermal voltage of the bipolar transistors. The temperature compensated control circuit preferably comprises a proportional to absolute temperature (PTAT) current source, and a steering pair of transistors connected to the PTAT current source and the pair of bipolar current switching transistors. The PTAT current source and steering transistors effectively bias the current switching transistors to account for the thermal voltage of the bipolar transistors.

Abstract: A bridge-configured precision voltage reference circuit includes a first voltage supply terminal, a second voltage supply terminal, first and second bridge nodes, and a bridge resistor connected between the first and second bridge nodes. A Zener diode is coupled between the first bridge node and the first voltage supply terminal, and a voltage divider circuit is coupled between the first voltage supply terminal and the second bridge node. An output voltage terminal is coupled to the voltage divider circuit, so that a precision output voltage is derived as a fraction of the voltage differential between the second bridge node and the potential of the first voltage supply terminal. A fixed magnitude current source is coupled between the first bridge node and the second voltage supply terminal, and an adjustable current source is coupled between the second voltage supply terminal and the second bridge node.

Abstract: A converter including an even and an odd digital-to-analog converter for converting digital signals from a successive approximation circuit and controlling the odd and even converters and the analog-to-digital converter device to alternate conversion by the even and odd converters. The odd and even converters operate in oppostie phases such that while one is in an acquisition phase the other is in a conversion phase. Each of the odd and even converters includes a separate coarse digital-to-analog converter and a common fine digital-to-analog converter. The control circuit resets the fine digital-to-analog converter during an initial portion of the conversion phase of each of the coarse digital-to-analog converters. In a two stage flash converter, the first stage includes a single analog-to-digital converter and the second stage includes a single digital-to-analog converter and alternatingly operating even and odd analog-to-digital converters.

Abstract: A single supply, TTL-compatible, class A-B signal buffer architecture comprises a multistage emitter-follower transistor circuit that is coupled between an input terminal and an output terminal capable of sinking and sourcing current to TTL specifications. A reference emitter-follower transistor stage is coupled in parallel with one of the emitter-follower transistor stages of the multistage emitter-follower transistor circuit, and a common emitter, current control transistor stage has its emitter-collector path coupled between the output terminal and ground for controlling the operation of the multistage emitter-follower transistor circuit. A differential amplifier stage, one arm of which is used to controllably forward bias the base-emitter junction of the current control transistor, has a first input coupled to the reference emitter-follower transistor stage and a second input coupled to the one emitter-follower transistor stage of the multistage emitter-follower transistor circuit.

Abstract: The feedback control loop of the common-emitter output transistor stage of a low dropout voltage regulator imcorporates a staggered pole-zero network, which effectively introduces an incremental reduction, or rolloff, in gain, and an accompanying reduction in phase shift with increase in frequency, so that, at the unity gain point of the transfer characteristic, there is still substantial phase margin, thus preventing the circuit from being driven into oscillation. The RC load pole location can vary widely and stability is maintained. The network is configured as a staggered resistor-capacitor network comprised of plural resistor-capacitor circuits coupled in cascade between the output of the feedback error amplifier and the input of a buffer amplifier the output of which drives the base of the output stage transistor in order to offset loading effects of the transistor base on the staggered pole-zero network.