Patents by Inventor Bruce J. Whitefield

Bruce J. Whitefield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7930655
    Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: April 19, 2011
    Assignee: LSI Corporation
    Inventors: ChandraSekhar Desu, Nima A. Behkami, Bruce J. Whitefield, David A. Abercrombie, David J. Sturtevant
  • Patent number: 7598127
    Abstract: A method of forming a carbon nanotube fuse by depositing a carbon nanotube layer, then depositing a cap layer directly over the carbon nanotube layer. The cap layer is formed of a material that has an insufficient amount of oxygen to significantly oxidize the carbon nanotube layer under operating conditions, and is otherwise sufficiently robust to protect the carbon nanotube layer from oxygen and plasmas. A photoresist layer is formed over the cap layer, and the photoresist layer is patterned to define a desired size of fuse. Both the cap layer and the carbon nanotube layer are completely etched, without removing the photoresist layer, to define the fuse having two ends in the carbon nanotube layer. Just the cap layer is etched, without removing the photoresist layer, so as to reduce the cap layer by a desired amount at the edges of the cap layer under the photoresist layer, without damaging the carbon nanotube layer.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: October 6, 2009
    Assignee: Nantero, Inc.
    Inventors: Bruce J. Whitefield, Derryl D. J. Allman, Thomas Rueckes, Claude L. Bertin
  • Publication number: 20080216048
    Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
    Type: Application
    Filed: May 8, 2008
    Publication date: September 4, 2008
    Applicant: LSI CORPORATION
    Inventors: ChandraSekhar Desu, Nima A. Behkami, Bruce J. Whitefield, David A. Abercrombie, David J. Sturtevant
  • Patent number: 7395522
    Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: July 1, 2008
    Assignee: LSI Corporation
    Inventors: ChandraSekhar Desu, Nima A. Behkami, Bruce J. Whitefield, David A. Abercrombie, David J. Sturtevant
  • Patent number: 7315360
    Abstract: A method for creating a reference for a first position on a substrate edge. A first reference point is selected relative to a circumference of the substrate edge, and a second reference point is selected relative to a bevel of the substrate edge. A first distance along the circumference of the substrate edge between the first reference point and the first position is identified as a first coordinate, and a second distance along the bevel of the substrate edge between the second reference point and the first position is identified as a second coordinate. The first coordinate and the second coordinate are used as the reference for the first position.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: January 1, 2008
    Assignee: LSI Logic Corporation
    Inventors: Bruce J. Whitefield, Jason W. McNichols
  • Patent number: 7277813
    Abstract: A method for selecting test site locations on a substrate, by a) specifying a subset of all test site locations on the substrate, and b) selecting a desired number of candidate test site locations from within the subset of test site locations on the substrate. c) While selecting one of the candidate test site locations and holding all others of the candidate test site locations as fixed, determining a new location for the selected one of the candidate test site locations, which new location increases a test sensitivity, as estimated by a trace of a variance-covariance matrix. d) Repeating step (c) for each candidate test site location in the subset of test site locations, to produce a finalized set of candidate test site locations, until a desired end point is attained.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: October 2, 2007
    Assignees: State of Oregon University Portland State, LSI Corporation
    Inventors: Bruce J. Whitefield, Paul J. Rudolph, James N. McNames, Byungsool Moon
  • Patent number: 7183181
    Abstract: A method of removing an edge bead of a coated material on a substrate. The substrate is rotated, and a fluid that solvates the coated material is delivered. The delivery of the fluid is directed radially inward on the substrate at a rate of between about three millimeters per second and about twenty millimeters per second until a desired innermost fluid delivery position on the substrate is attained. Immediately upon attaining the desired innermost fluid delivery position on the substrate, the delivery of the fluid is directed radially outward off the substrate at a rate of more than zero millimeters per second and less than about four millimeters per second. The rotation of the substrate is ceased.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: February 27, 2007
    Assignee: LSI Logic Corporation
    Inventors: Xiao Li, Roger Y. B. Young, Bruce J. Whitefield
  • Patent number: 7137098
    Abstract: A method for determining component patterns of a raw substrate map. A subset of substrate patterns is selected from a set of substrate patterns, and combined into a composite substrate map. The substrate patterns are weighted. The composite substrate map is compared to the raw substrate map, and a degree of correlation between the composite substrate map and the raw substrate map is determined. The steps are iteratively repeated until the degree of correlation is at least a desired degree, and the weighted subset of substrate patterns is output as the component patterns of the raw substrate map.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: November 14, 2006
    Assignee: LSI Logic Corporation
    Inventors: Bruce J. Whitefield, David A. Abercrombie, David R. Turner, James N. McNames
  • Patent number: 7062415
    Abstract: A method for determining outlier data points in. A subset of dataset patterns is selected from a set of mathematical dataset patterns, and the subset of dataset patterns is combined into a composite dataset. The composite dataset is compared to the dataset, and a degree of correlation between the composite dataset and the dataset is determined. Data points within the composite dataset are selectively weighted to improve the degree of correlation, and the steps described above are selectively iteratively repeated until the degree of correlation is at least a desired value. Residuals for the data points within the composite dataset are selectively determined. At least one of the weighted data points within the composite dataset that are weighted within a first specified range, and data points within the composite dataset that have a residual within a second specified range, are selectively output as outlier data points.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: June 13, 2006
    Assignee: LSI Logic Corporation
    Inventors: Bruce J. Whitefield, David A. Abercrombie, David R. Turner, James N. McNames
  • Patent number: 7039556
    Abstract: A system for analyzing fabrication processes, such as analyzing device yield on a substrate. An input accesses fabrication information, where the fabrication information includes at least one of an dependent variable that is associated with substrate location information, and at least one independent variable that is associated with at least one of the fabrication processes. Desired portions of the substrate information are selected, based on at least one of the independent variable and the dependent variable. A substrate profile is produced, based on the desired portions of the fabrication information.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: May 2, 2006
    Assignee: LSI Logic Corporation
    Inventors: Bruce J. Whitefield, David A. Abercrombie
  • Patent number: 7013192
    Abstract: A method of analyzing substrate yield, where a substrate yield map and a substrate contact map are selected and overlaid to produce a composite map. First elements of the substrate yield map are compared to second elements of the substrate contact map to determine a degree of correlation between the first elements and the second elements. Additional substrate contact maps are repeatedly selected and the first elements of the substrate yield map are compared to the second elements of the additional substrate contact maps, and a degree of correlation between the first elements and each of the second elements for the additional substrate contact maps is determined and reported. The composite map having a highest degree of correlation between the first elements and the second elements is presented, and all composite maps that have at least a desired degree of correlation between the first elements and the second elements are presented.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: March 14, 2006
    Assignee: LSI Logic Corporation
    Inventors: Bruce J. Whitefield, David A. Abarcrombie
  • Patent number: 6645857
    Abstract: A method of forming an electrically conductive via that abuts a key hole formed in filler material. A void is etched through the filler material in which the key hole is formed, thereby forming a link between the void and the key hole. A liner is formed within the void, where the liner is formed to a thickness that is at least about half a minimum cross sectional dimension of the key hole, so as to plug the link between the void and the key hole and thereby trap any contaminants within the key hole. Electrically conductive via material is deposited within the void to form the via.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: November 11, 2003
    Assignee: LSI Logic Corporation
    Inventors: Bruce J. Whitefield, Ashwin Ramachandran
  • Patent number: 6512985
    Abstract: A computerized system for analyzing information associated with a process unit. A database contains historical information relating to previously compiled information. A secure input receives criteria from a restricted source. A computer mathematically determines a limit based upon the criteria. An open input receives the information associated with the process unit from multiple test locations. A compiler selectively adds to the database of historical information the information. The computer also selects at least a portion of the information based upon selection criteria. In addition, the computer manipulates the selected information based upon manipulation criteria. The manipulated information is compared against the limit. An output indicates a first disposition of the process unit when the manipulated information violates the limit. The output indicates a second disposition of the process unit when the manipulated information does not violate the limit.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: January 28, 2003
    Assignee: LSI Logic Corporation
    Inventors: Bruce J. Whitefield, Manu Rehani, John A. Knoch