Abstract: Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.

Abstract: Methods, apparatus, and products for optimizing delivery of regulated power from a voltage regulator to an electrical component, operation of the voltage regulator controlled by a service processor, the voltage regulator including a number of phases, each phase rated to deliver a different maximum power to the electrical component, where optimizing delivery of regulated power includes determining, by the service processor, the present power requirements of the electrical component, and enabling, by the service processor, one or more phases of the voltage regulator in dependence upon the present power requirements of the electrical component.

Abstract: Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.

Abstract: Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.

Abstract: Cables and methods of manufacturing cables for high speed data communications, the cable including: a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers parallel with and along a longitudinal axis; and folded conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps along and about the longitudinal axis, the conductive shield material comprising a first conductive layer and second conductive layer separated by an inner-shield dielectric layer.

Abstract: In one embodiment, a fan is used to generate airflow through a computer chassis to a fan air inlet. An audible frequency component of the airflow is identified and selected. A sound wave is generated having a generated frequency equal to the selected audible frequency component of the airflow. The generated sound wave is introduced into the airflow with the generated frequency out of phase with the audible frequency component of the airflow. The magnitude of the generated frequency may be selected as a function of fan speed and/or air sensed pressure within the airflow. The frequency, phase, and magnitude of the generated sound wave may be selected and enforced by a baseboard management controller.

Abstract: Cables and methods of manufacturing cables for high speed data communications, the cable including: a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers parallel with and along a longitudinal axis; and folded conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps along and about the longitudinal axis, the conductive shield material comprising a first conductive layer and second conductive layer separated by an inner-shield dielectric layer.

Abstract: Methods, apparatus, and products for optimizing delivery of regulated power from a voltage regulator to an electrical component, operation of the voltage regulator controlled by a service processor, the voltage regulator including a number of phases, each phase rated to deliver a different maximum power to the electrical component, where optimizing delivery of regulated power includes determining, by the service processor, the present power requirements of the electrical component, and enabling, by the service processor, one or more phases of the voltage regulator in dependence upon the present power requirements of the electrical component.

Abstract: Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.

Abstract: A cable for high speed data communications and methods for manufacturing such cable are disclosed, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The cable also includes conductive shield material wrapped in a rotational direction at a wrap rate along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps of the conductive shield material along and about the longitudinal axis, an inner surface of the conductive shield material roughened to reduce non-linear attenuation of signals transmitted through the conductive shield material. Transmitting signals on the cable including transmitting a balanced signal characterized by a frequency in the range of 7-9 gigahertz on the cable.

Abstract: Embodiments of the invention address deficiencies of the art in respect to power sequencing, and provide a method, system and computer program product for supporting coupling with independent logic circuits. In one embodiment of the invention, a computer system supporting coupling with independent logic circuits may include an independent logic circuit including at least one voltage regulator that regulates voltage to core logic such that voltage is transferred to the core logic upon receiving a first level of voltage. The independent logic circuit may further include an I/O driver that becomes operational upon receiving a highest level of voltage higher than the first level of voltage. The computer system may further include a voltage ramp for transferring voltage to the independent logic circuit at the first level voltage for a predetermined period of time and subsequently at the highest level of voltage.

Abstract: A Twinax cable include a first axial cable having an inner diameter portion and an outer diameter portion and including a conductor surrounded by a dielectric material. A second axial cable has an inner diameter portion and an outer diameter portion and including a conductor surrounded by a dielectric material, the second axial cable being arranged such that a portion of the inner diameter thereof contacts the inner diameter portion of the first axial cable. A drain conductor is disposed between at least a portion of the inner diameter portion of the first axial cable and the inner diameter portion of the second axial cable. In addition, the a first foil layer contacts at least a portion of the outer diameter portion of the first axial cable and a second foil layer contacts at least a portion of the outer diameter portion of the second axial cable. An outer foil layer surrounds the first ax cable, the second axial cable, the first foil layer and the second foil layer.

Abstract: Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.

Abstract: Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.

Abstract: In a printed circuit board having a plural number of conductor layers separated by a plural number of insulator layers, a Faraday cage is constructed including a first and a second ground plane disposed in a first and second conductor layer respectively. The ground planes being electrically interconnected at their peripheries, preferably by a plurality of vias. A third conductor layer is disposed between the first and second conductor layers in which a plurality of signal paths are defined. The Faraday cage surrounds a shielded portion of the third conductor layer so that electrical signals conducted through the shielded portion are isolated from electrical noise.

Abstract: In a printed circuit board having a plural number of conductor layers separated by a plural number of insulator layers, a Faraday cage is constructed including a first and a second ground plane disposed in a first and second conductor layer respectively. The ground planes being electrically interconnected at their peripheries, preferably by a plurality of vias. A third conductor layer is disposed between the first and second conductor layers in which a plurality of signal paths are defined. The Faraday cage surrounds a shielded portion of the third conductor layer so that electrical signals conducted through the shielded portion are isolated from electrical noise.

Abstract: An apparatus for transmitting an analog image signal representing an image over a bus including a driver circuit which receives a single ended analog image signal from a media source and provides a differential analog image signal and a switch circuit which selectively provides the differential analog image signal to the bus in response to control information.

Abstract: In a printed circuit board having a plural number of conductor layers separated by a plural number of insulator layers, a Faraday cage is constructed including a first and a second ground plane disposed in a first and second conductor layer respectively. The ground planes being electrically interconnected at their peripheries, preferably by a plurality of vias. A third conductor layer is disposed between the first and second conductor layers in which a plurality of signal paths are defined. The Faraday cage surrounds a shielded portion of the third conductor layer so that electrical signals conducted through the shielded portion are isolated from electrical noise.

Abstract: A MIDI/joystick breakout box is described which incorporates a shielded connector, a shielded cable, and a terminal block including a circuit board with an extensive ground plane surrounding the joystick connections and shielding the MIDI circuitry on at least three sides. The terminal block is a housing which acts as a radiation shield. The housing or terminal block may be made of an injected molded plastic material containing electrically conductive strands of metal or the housing may be plated or painted on its interior surfaces with an electrically conductive material to form a shielding layer which may then be further connected to the ground plane of the electronic circuit board contained within the terminal block housing. The terminal block provides connectors for MIDI-In, MIDI-Out MIDI-Thru and a pair of joystick interface connectors which allows the capability to connect both MIDI devices and two joysticks to the audio adapter card simultaneously.

Abstract: A multimedia solution is presented which allows a multimedia architecture to be implemented on an existing computer system. According to the invention, an expansion unit which incorporates a multimedia architecture is provided. The expansion unit is connected to an existing computer system via an expansion slot of an I/O bus of the existing computer as well as via a display device output terminal of the computer. The expansion unit is also connected to a display device. Accordingly, the expansion unit controls the presentation which is provided on the display device.