Abstract: A plurality of status reporting units are connected respectively to a plurality of shift registers. The shift registers receive and store status signals from the status reporting units. Each of the shift registers include an OR circuit for combining the signals from all of the stages of the respective shift registers. An output of the OR circuit is connected to the input of one stage of a shift register other than the shift register supplying signals thereto. The arrangement is such that the one stage in the respective shift registers indicate the status of one or more error status reporting units. A status analyzing unit receives signals from the various shift registers for analyzing error patterns of the status reporting units in response to receiving a signal that at least one of the status reporting units has error status to report.