Abstract: There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 ?m in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation. The method, in examples, includes thinning the nanowire through iterative oxidation and etching of the oxidized portion.

Abstract: A radiation detector comprises a silicon body in which are defined vertical pores filled with a converter material and situated within silicon depletion regions. One or more charge-collection electrodes are arranged to collect current generated when secondary particles enter the silicon body through walls of the pores. The pores are disposed in low-density clusters, have a majority pore thickness of 5 ?m or less, and have a majority aspect ratio, defined as the ratio of pore depth to pore thickness, of at least 10.

Abstract: There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 ?m in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation.

Abstract: The various technologies presented herein relate to a three dimensional manufacturing technique for application with semiconductor technologies. A membrane layer can be formed over a cavity. An opening can be formed in the membrane such that the membrane can act as a mask layer to the underlying wall surfaces and bottom surface of the cavity. A beam to facilitate an operation comprising any of implantation, etching or deposition can be directed through the opening onto the underlying surface, with the opening acting as a mask to control the area of the underlying surfaces on which any of implantation occurs, material is removed, and/or material is deposited. The membrane can be removed, a new membrane placed over the cavity and a new opening formed to facilitate another implantation, etching, or deposition operation. By changing the direction of the beam different wall/bottom surfaces can be utilized to form a plurality of structures.

Abstract: A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Abstract: The present invention includes a method and apparatus for the rapid, nondestructive evaluation of the contrast of a latent image in a photoresist. More particularly, the contrast of the latent image is directly monitored by measuring the intensity of the light diffracted from a pattern in the exposed, undeveloped photoresist known as the latent image. The proper exposure tool parameters, such as exposure tool time and focus, is suitably determined based on the intensity of different orders of diffracted light, namely the 2nd-order diffracted from the latent image. In a preferred embodiment, a test pattern consisting of a periodic pattern, or a pattern of the device associated with the particular lithographic step, is employed to provide well-defined diffraction orders.

Abstract: Multiple-exposure fine-line interferometric lithography, combined with conventional optical lithography, is used in a sequence of steps to define arrays of complex, nm-scale structures in a photoresist layer. Nonlinearities in the develop, mask etch, and Si etch processes are used to modify the characteristics and further reduce the scale of the structures. Local curvature dependent oxidation provides an additional flexibility. Electrical contact to the quantum structures is achieved. Uniform arrays of Si structures, including quantum wires and quantum dots, are produced that have structure dimensions on the scale of electronic wave functions. Applications include enhanced optical interactions with quantum structured Si, including optical emission and lasing and novel electronic devices based on the fundamentally altered electronic properties of these materials. All of the process sequences involve parallel processing steps to make large fields of these quantum structures.