Abstract: A system and method for determining an initial duty cycle for startup of a voltage regulator involves generating a first current source responsive to an input voltage to the voltage regulator and generating a second current source responsive to an output voltage of the voltage regulator. A first capacitor is charged using the first current source responsive to a duty cycle of a PWM signal of the voltage regulator to a first voltage. A second capacitor is charged to a second voltage responsive to a period of the PWM signal of the voltage regulator. The initial duty cycle for startup of the voltage regulator is established as the duty cycle of the PWM signal when the first voltage is substantially equal to the second voltage.

Abstract: A system and method for determining an initial duty cycle for startup of a voltage regulator involves generating a first current source responsive to an input voltage to the voltage regulator and generating a second current source responsive to an output voltage of the voltage regulator. A first capacitor is charged using the first current source responsive to a duty cycle of a PWM signal of the voltage regulator to a first voltage. A second capacitor is charged to a second voltage responsive to a period of the PWM signal of the voltage regulator. The initial duty cycle for startup of the voltage regulator is established as the duty cycle of the PWM signal when the first voltage is substantially equal to the second voltage.

Abstract: A method for starting up a voltage-mode switching power supply into a biased load includes computing a ratio of the load voltage at the biased load to an input voltage of the switching power supply, generating a first signal indicative of the duty cycle of the voltage-mode switching power supply, comparing the first signal indicative of the duty cycle to the ratio, and turning on an output stage of the voltage-mode switching power supply only when the first signal indicative of the duty cycle is equal to the ratio. In this manner, the voltage-mode switching power supply can be started up to supply power to a biased load without dragging down the load voltage of the biased load.

Abstract: A dual mode regulator, having a high current PWM regulator mode and a low current LDO regulator mode, briefly changes the operating parameters of the PWM and LDO regulators during a transition between modes. Changes during the transition period include: raising the error amplifier reference voltage of the LDO or PWM regulator to ensure a definite handover, raising the bias current in the LDO stages during the transition to cause the LDO regulator to quickly and stably respond to voltage glitches, and augmenting the LDO regulator series pass transistors with one or more additional pass transistors during the transition to enable the LDO regulator to handle higher currents. After the transition, the operating parameters of the enabled regulator portion are reset to their nominal values. The PWM regulator is started with a soft start routine to limit current through the power transistor.

Abstract: A resistance multiplier circuit coupled to a first node of a first circuit for providing a high-value resistance at the first node includes a first transistor, a second transistor being N times larger than the first transistor, and a resistor. In one embodiment, the first and second transistors are NPN bipolar transistors. The first transistor has its base and collector terminals coupled to the first node and an emitter terminal coupled to a second node. The second transistor has a base terminal coupled to the first node, a collector terminal coupled to a positive supply voltage, and an emitter terminal coupled to the second node. The resistor is coupled between the second node and a virtual ground node. When a voltage is applied to the first node, the resistance at the first node is (N+1) times the resistance of the resistor.

Abstract: A switching regulator includes a compensation circuit for applying a scaling factor to the loop gain of the feedback control loop of the regulator. In operation, the loop gain of the feedback control loop has a dependency on the input and output voltages of the switching regulator. The compensation circuit applies a function as the scaling factor where the function is a reciprocal function of the loop gain dependency on the input voltage and output voltage. In one embodiment, the loop gain has a dependency on the ratio VIN/VOUT and a scaling factor having a value indicative of the ratio VOUT/VIN is applied by the compensation circuit. In one embodiment, the compensation circuit is coupled in series with the output circuit of an error amplifier in the feedback control loop of the regulator. In another embodiment, the compensation circuit is subsumed within the circuitry of the error amplifier.

Abstract: A current mode switching regulator implementing a dual sense scheme includes a first current sensing circuit for sensing a current through a first switch and providing a first current sense signal, and a second current sensing circuit for sensing a current through a second switch and providing a second current sense signal. The switching regulator includes a control circuit for generating switch control signals for driving the first and second switches in response to one of the first and second current sense signals. The regulator further includes a duty cycle detection circuit coupled to determine a duty cycle of the switching regulator. The detection circuit asserts a first select signal to select the first current sense signal when the duty cycle exceeds a first threshold level and asserts a second select signal to select the second current sense signal when the duty cycle is less than a second threshold level.

Abstract: A resistance multiplier circuit coupled to a first node of a first circuit for providing a high-value resistance at the first node includes a first transistor, a second transistor being N times larger than the first transistor, and a resistor. In one embodiment, the first and second transistors are NPN bipolar transistors. The first transistor has its base and collector terminals coupled to the first node and an emitter terminal coupled to a second node. The second transistor has a base terminal coupled to the first node, a collector terminal coupled to a positive supply voltage, and an emitter terminal coupled to the second node. The resistor is coupled between the second node and a virtual ground node. When a voltage is applied to the first node, the resistance at the first node is (N+1) times the resistance of the resistor.

Abstract: A system and method for detecting brown-out conditions in a microcontroller, enabling a user to program the brown out detection system, and distinguishing between real brown-out events and transitory voltage swings without requiring expensive and time consuming logic. The invention compares a sense voltage to a reference voltage and filters the resulting signal to distinguish between a true-brown out signal and transitory voltage swings. The invention uses one or more program bits that vary the ratio of the supply voltage and the sense voltage. That is, the sense voltage is programmable and is dependent upon the value of the supply voltage and the value of the program bits. The present invention generates a comparison output signal based upon the comparison of the supply voltage and the sense voltage. The comparison output signal is filtered to distinguish between a real brown-out event and transitory voltage swings.

Abstract: A system and method for ensuring a substantially constant oscillator frequency that is substantially independent of the operating temperature and is substantially independent of variations of the supply voltage level where the oscillator is an on-chip oscillator without requiring significantly additional logic, e.g., not requiring the use of multiple comparators and enabling post packaging modifications of the oscillator frequency. The present invention utilizes one or more paired resistors as part of the RC oscillator where each of the one or more pairs are matched according to their temperature coefficient. That is, each pair includes a resistor with a positive temperature coefficient and a resistor with a corresponding negative temperature coefficient. In addition, the present invention enables post packaging modifications to the resistors based upon one or more program signals that can modify the resistance by forming a short circuit around one or more resistor pairs.

Abstract: An architecture for producing multiple emitter vertical bipolar transistors which substantially eliminates the starved regions found in the standard lattice architecture. An "offset lattice" design is described in which the base contact segments in adjacent stripes are shifted or offset relative to each other. This causes the emitter pieces which are added to connect adjacent emitter stripes to be staggered with respect to each other. As a result, all sections of the emitters face a base contact and the resistance encountered along a current path between a base contact and an emitter is reduced. This results in a vertical bipolar transistor having a larger proportion of highly activated emitter, better high-frequency performance, and a reduction in thermal noise owing to transistor base resistance.

Abstract: An architecture for producing multiple emitter vertical bipolar transistors which substantially eliminates the starved regions found in the standard lattice architecture. An "offset lattice" design is described in which the base contact segments in adjacent stripes are shifted or offset relative to each other. This causes the emitter pieces which are added to connect adjacent emitter stripes to be staggered with respect to each other. As a result, all sections of the emitters face a base contact and the resistance encountered along a current path between a base contact and an emitter is reduced. This results in a vertical bipolar transistor having a larger proportion of highly activated emitter, better high-frequency performance, and a reduction in thermal noise owing to transistor base resistance.